Symmetric transparent online BIST for arrays of word-organized RAMs

Abstract

Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. Previous works on symmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach, given the large number of memories available in current chips, increases the hardware overhead of the BIST circuitry. In this work we propose a Symmetric transparent BIST scheme that can be utilized to test RAMs of different word widths; hence, more than one RAMs can be tested in a roving manner. The hardware overhead of the proposed scheme is considerably smaller compared to the utilization of previously proposed symmetric transparent schemes, for typical memory configurations.