Abstract
A novel design is exhibited in the paper presented here for an analog-to-digital converter (ADC) built-in self test (BIST) scheme using code-width technique. An 8-bit sigma-delta ADC BIST scheme is introduced. The 8 bit sigma-delta ADC with arbitrary faults is simulated in the given BIST scheme designed in CMOS 45nm technology. Different parametric faults have been detected here such as Differential Non Linearity (DNL), monotonicity fault and missing code fault. This architecture of ADC BIST is achieved by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology. The power dissipation of the BIST circuit is 18mW for the power supply of 1V.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
