A built in self test scheme for 256Meg sdram

Abstract

This paper presents a Built In Self Test (BIST) scheme for very high parallelism memory testing to be done on a BIST Board with DC stimuli. A BIST scheme with ten algorithms was implemented on a 256Meg, 4 banks, X32 SDRAM. Self Test operation is synchronized by an on chip oscillator which also generates internal timing signals needed for memory testing. Various ways to test the functionality of BIST circuitry as well as some engineering and debug features are also included.