Build-up Layer Research Articles

Novel Chip-Last Method for Embedded Actives in Organic Packaging Substrates

Embedded actives are to bury thinned active chips into package substrates, as opposed to surface mounted devices (SMDs), which can achieve smaller form factor, better electrical performance and higher functionality than the SMD technology. While many embedded actives have been explored so far, they are based on chip-first and -middle approaches, in which the active chips are embedded before and during the build-up processes of package substrates, respectively. The most concern with those two current approaches is the loss accumulation associated with the build-up layer processes carried out right on top of the embedded chips, which is highly likely to lose the embedded chips during their packaging process. The reworkability to replace the faulty chips embedded with good ones and thermal management of the embedded chips are also issues since the embedded chips are totally surrounded by hard-cured polymers. In this paper, chip-last embedded active has been proposed to address some of the issues that are reported in current chip-first and -middle approaches, in which chips are embedded after all the package substrate processes including the build-up layers are completed, just like conventional SMD packaging. In the chip-last approach, a cavity is introduced within the build-up layers of package substrate and a chip is directly embedded into the cavity. A first proto-type of the chip-last embedded active will be demonstrated by developing various cavity formation processes within the build-up layers and then embedding 100 μm thick chips into the defined cavities.

Advanced Surface Laminar Circuits Using Newly Developed Resins

This paper introduces a newly developed advanced surface laminar circuit (Adv-SLC) packaging technology, which utilizes new composite materials. Adv-SLC is a build-up substrate technology designed to fulfill the requirements of the most advanced semiconductor chips. Our new dielectric material is a build-up layer composed of two different materials. We also used a new material for the core substrate, composed of liquid crystalline polymer reinforced with glass cloth. The build-up layer has the following, highly reliable properties: it can maintain both conductivity and dielectricity under the conditions of both a line/space width of 10/10 μm and a via diameter of 30 μm . The core substrate also has excellent, reliable properties: it can maintain both conductivity and dielectricity under the conditions of a through hole diameter of 60 μm and a through hole pitch of 120 μm. We were able to confirm that the formation of the new substrate with the aforementioned new design rules contributes to reduce the size of the silicon chip. Consequently, Adv-SLC contributes to reduce thermal stress when mounting a flip chip.

Tribological investigation on friction and wear behaviour of coatings for hot sheet metal forming

Abstract Since hot sheet metal forming has become a key technology to produce high strength steel parts for modern automotive construction, detailed knowledge of tribological behaviour of coated steel blanks at elevated temperatures is necessary. Therefore, hot dip aluminium–silicium and electro-plated zinc alloy coatings for hot forming applications have been evaluated according to their friction and wear behaviour. The coefficient of friction was revealed in hot strip drawing experiments. Moreover, mass loss of the workpiece has been measured to characterize the amount of wear. According to the different constitution of the Al–Si coating in comparison to the electro-plated Zn–Ni after heat treatment, the zinc alloy coating showed higher mass loss but lower coefficient of friction. Additionally, wear characteristics have been evaluated in hot forming tests. Herein, parts formed of Al–Si coated blanks showed as well a lower mass loss but more aggressive wear behaviour by means of adhesive wear to the die, resulting in metallic build-up onto the die radius. In contrast, the workpiece related mass loss was higher for Zn–Ni but considerable metallic build-up layers onto the die did not occur. This may be advantageous in production lines hence maintenance and reconditioning frequency of the forming tools could be reduced.

Impact of Process Improvements on Reliability of RCP Technology During Scale-up

The start-up of the 300mm RCP prototype production line using automated tools was challenged by significant differences in tool sets when compared to the manual and semi-automatic lab based equipment used to develop the baseline RCP fabrication process. Thus, process transfer to automated tools required key parameter adjustments in an attempt to match the process output and reliability performance previously achieved with the 200mm lab based flow. During reliability testing of early parts from the 300mm prototype line, failures in the build-up layers were observed after thermal cycling test. The failure mechanisms were previously observed and resolved during the technology development phase using the 200mm lab based tools. An experiment was developed to identify the root cause of the build-up failures. A single die, 9x9mm, 258 I/O, 0.5mm pitch package with 2 metal routing layers was chosen as a test vehicle for the experiment. Moisture preconditioning and air to air thermal cycling at 2 different conditions followed by electrical test and visual inspection for dielectric cracks were used to gage reliability performance. Several factors were evaluated related to the dielectric and metallization processes as well as the backend interconnect process. The results from the experiment indicated the appropriate tool parameters that allowed the 300mm prototype line process output to closely match that of the 200mm lab based tools. The optimized process combined with the use of an alternate solder material allowed the 300mm RCP prototype line to successfully achieve line certification status and demonstrated RCP reliability performance beyond standards.

Embedded Active Packaging Technology for High-Pin-Count LSI With Cu Plate

We have developed a thin, reliable, low-thermal-resistance LSI packaging technology by embedding a high-pin-count LSI chip into thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 μm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics of only 34 μm at room temperature for 27 × 27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in size. It is also possible to reduce the total package thickness to 0.46 mm by etching the Cu plate to half thickness, with keeping the warpage increase up to 117 μm. Low thermal resistance of 10.8°C/W is achieved for the packages with 0.5-mm-thick Cu plate at a wind velocity of 0 m/s, which is almost comparable to that of an FCBGA with a large heat sink. We have successfully demonstrated the functions of our packages using an LSI tester and personal-computer-like system board. They have also passed a 1000-cycle package-level thermal cycle test.

Realization of Power Modules by Chip Embedding Technology

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology, which is based on printed circuit board manufacturing processes, and will also demonstrate the transfer of the technology from a smaller size lab scale equipment environment to an industrial comparable process line, capable of processing large panel formats up to 18” x 24”. The paper will also briefly describe this development and categorize today's embedding technologies. First modules with embedded chips are in production in Asia, mainly for telecom and computer applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. In a number of European cooperation projects with partners from industry and research, embedding of power chips, like IGBTS and power MOSFET, is of high interest. In this paper current achievements of these projects will be shown, especially examples of realized devices and their characteristics. The dominating technology for power chip embedding is a face-up technology. Chips are bonded with their backside (drain contact) to a Cu substrate using highly conductive adhesive or solder. Using the face up assembly, a direct contact to the backside of the die is possible, allowing a lot of benefits for driving high currents and applying an efficient thermal management for the power devices. Then Chips are embedded by vacuum lamination of prepreg or RCC (resin coated copper) layers. Via holes to the top contacts (gate and source) are formed by laser drilling. The vias are metallized using conventional Cu plating. Finally conductor structures are etched in the top Cu layer, finalizing the circuit. Details will be given about device manufacturing, related yield issues and strategies to overcome them. Finally scenarios for the implementation of embedding technology and concepts for future applications will be discussed.

Experimental and theoretical studies on stainless steel transfer onto a TiN-coated cutting tool

Stainless steel is a good example of a metal that is not easily machined. To explain such behavior an understanding of the fundamental adhesion between the workpiece and the tool is invaluable. It is a well-known fact that build-up layers form in the interface, but little attention has been given to the very first layer that adheres to the tool surface. Although this layer rapidly becomes covered by successive material transfer, this layer and its ability to stick to the tool surface control the successive material transfer and influence the cutting properties. In this work, a quick stop test is employed to interrupt the cutting of a 316L stainless steel using a TiN-coated cemented carbide cutting insert. Different analytical techniques, such as transmission electron microscopy, X-ray photoelectron spectroscopy and scanning electron microscopy, as well as theoretical atomistic modeling, were used to study the early adhesion.

Next Generation System in a Package Manufacturing by Embedded Chip Technologies

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and thereby the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial quad flat packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm, and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (resin coated copper) layers by using vacuum lamination. The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10 × 10 mm2. All embedded chip QFN packages at the prototype level are manufactured in 250 × 300 mm2 panels.

Nanomaterials for “Green” Electronics

This paper examines the use of nanomaterials in the area of “green” technology. A variety of green materials for advanced organic packaging have been developed. These include capacitors and resistors as embedded passives, resin coated Cu (RCC) as buildup layers, highly conducting nano-micro media for Z-interconnects, lead free assembly paste, ZnO based additives, magnetic materials, inductors and thermal interface materials (TIM). Nanocomposites can provide high capacitance densities, ranging from 5 nf/inch2 to 25 nF/inch2, depending on composition, particle size and film thickness. The electrical properties of capacitors fabricated from BaTiO3-epoxy nanocomposites showed a stable capacitance over a temperature range from 20°C to 120 °C. A variety of printable discrete resistors with different sheet resistances, ranging from 1 ohm to 120 Mohm, processed utilizing a large panel format (19.5 × 24 inches) have been fabricated. Low resistivity nanocomposites, with volume resistivity in the range of 10−4 ohm-cm to 10−6 ohm-cm depending on composition, particle size, and loading can be used as conductive joints for high frequency and high density interconnect applications. A variety of metals including Cu, Ag, LMP (low melting point) and LMP-coated Cu fillers have been used to make halogen free, lead free electrically conducting adhesive technology as an alternative to solders. Halogen free resin modified with ceramics/organic particles can produce low Dk resin coated Cu (RCC) with Dk value in the range between 4.2 and 2.5. Similarly, low loss RCC materials can be produced by combining HF resin with low loss fillers. The mechanical strength of the various RCC was characterized by a 90 degree peel test and measurement of tensile strength. RCC exhibited peel strength with Gould's JTC-treated Cu as high as 6 lbs/inch for halogen free RCC. These halogen free RCC materials exhibit coefficients of thermal expansion (CTE), ranging from 27 ppm/°C to 32ppm/°C. The paper also describes a nanoparticle dispersion approach to prepare nanogels and nanofluids as thermal interface materials. Altogether, this is a new direction in the development of Green Packages and more specifically in the development of coreless substrates for semiconductor packaging.

Next Generation System in a Package Manufacturing by Embedded Chip Technologies

The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology and more importantly it will focus on new efforts to actually use chip embedding concepts for the realization of standard-type industrial Quad Flat Packages with embedded chips (embedded chip QFN). Chips of 50 μm thickness, a pad pitch of 100 μm and pad size of 85 μm are die bonded to a copper substrate and subsequently embedded in RCC (Resin-Coated-Copper) layers by using vacuum lamination. The resulting QFN packages are only 160 μm thick and provide standard pads at 400 μm pitch and a total number of 84 I/Os with dimensions of 10x10 mm2. All embedded chip QFN packages at prototype level are manufactured in 250x300 mm2 panels. The present work will include QFN package reliability results after extensive testing of thermal cycling, temperature humidity, high temperature storage and pressure cooker test. The investigation of new embedding material combinations is one task to provide a reliable package. The main focus here is on new materials that offer improved package stability and also the ability to embed dies of different thickness. Together with material suppliers improved resin formulations as well as the introduction of filler and glass fibers into the resin layers is currently realized and tested. In order to realize a further miniaturization ultra fine pitch (UFP) and fine line (UFL) approaches will be presented. For a UFP approach the goal is to develop the laser via technology further towards their limits as well as the investigation of new concepts. UFP requires the use of a semi additive patterning process. Here LDI processing is being used for all new generation chip embedded packages due to its potential for very fine copper patterning. Results on very fine L/S of 15–20μm will be shown based on the semi-additive processes on an ultra thin initial 1–2μm copper foil. Finally different applications will be presented. In an industrial cooperation different power package developments are ongoing. Here single and multi chips modules are realized as well as multiple routing layers. The combination of power and logic is one of the main challenges here, due to the need of thick copper layers for the power part and the more fine pitch demands for the controller chips. Process developments and results will be discussed in detail.

Design, Fabrication, Electrical Characterization and Reliability of Nanomaterials Based Embedded Passives

This paper discusses thin film technology based on barium titanate (BaTiO3)-epoxy polymer nanocomposites. In particular, we highlight recent developments on high capacitance, large area, thin film passives and their integration in System in a Package (SiP). A variety of nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on PWB substrates by liquid coating or printing processes. SEM micrographs showed uniform particle distribution in the coatings. The electrical performance of composites was characterized by dielectric constant (Dk), capacitance and dissipation factor (loss) measurements. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. Cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. In another design, we have used eight layer high density internal core and subsequent fine geometry n (1 to 3) buildup layers to form a n-8-n structure. The eight layer internal core has two resistance layers in the middle and 2 to 6 capacitance layer sequentially applied on the surface. The study also evaluates the resistor materials for embedded passives. Resistors are carbon based pastes and metal based alloys NiCrAlSi. Embedded resistor technology can use either thin film materials, that are applied on the copper foil, or screened carbon based resistor pastes that can achieve any resistor value at any level. For example, combination of 25 ohm per square material and 250 ohm per square material enables resistor ranges from 15 ohms through 30,000 ohms with efficient sizes for the embedded resistors. Similarly, printable resistors can be designed to cover the resistance in the range of 5 ohms to 1 Mohm. The embedded resistors can be laser trimmed to a tolerance of &amp;lt;5% for applications that require tighter tolerance. Reliability of the test vehicles was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded discrete capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1400 cycles DTC (Deep Thermal Cycle).

Resin coated copper capacitive (RC3) nanocomposites for multilayer embedded capacitors: towards system in a package (SiP)

PurposeEmbedded passives account for a very large part of today's electronic assemblies. This is particularly true for products such as cellular phones, camcorders, computers, and several critical defence devices. Market pressures for new products with more features, smaller size and lower cost demand smaller, compacter, simpler substrates. An obvious strategy is to reduce the number of surface mounted passives by embedding them in the substrate. In addition, current interconnect technology to accommodate surface mounted passives imposes certain limits on board design which constrain the overall system speed. Embedding passives is one way to minimize the functional footprint while at the same time improving performance. The purpose of this paper is to describe the development of a thin film technology based on ferroelectric‐epoxy polymer‐based flake‐free resin coated copper capacitive (RC3) nanocomposites to manufacture multilayer embedded capacitors.Design/methodology/approachThis paper discusses thin film technology based on RC3 nanocomposites. In particular, recent developments in high capacitance, large area, thin film passives, and their integration in system in a package (SiP) are highlighted.FindingsA variety of RC3 nanocomposite thin films ranging from 8 to 50 microns thick were processed on copper substrates by liquid coating. Multilayer embedded capacitors resulted in high capacitances of 16‐28 nF. The fabricated test vehicle also included two embedded resistor layers with resistances in the range of 15 Ω to 100 kΩ. To enable high performance devices, an embedded resistor must meet certain tolerances. The embedded resistors can be laser trimmed to a tolerance of &lt;5 percent, which is usually acceptable for most applications. An extended embedded passives solution has been demonstrated, both through its high wireability designs and package performance, to be perfectly suited for SiP applications.Research limitations/implicationsThis case study designed and fabricated an eight layer high density internal passive core and subsequently applied fine geometry three buildup layers to form a 3‐8‐3 structure. The passive core technology is capable of providing up to six layers of embedded capacitance and could be extended further.Originality/valueA thin film technology based on ferroelectric‐epoxy polymer‐based flake‐free RC3 nanocomposites was developed to manufacture multilayer embedded capacitors. The overall approach lends itself to package miniaturization because capacitance can be increased through multiple layers and reduced thickness to give the desired values in a smaller area.

ON RADIOTHERAPY DOSE VERIFICATION WITH A FLAT-PANEL IMAGER

The purpose of this study was to investigate the dose-response characteristics, including ghosting effects, of an amorphous silicon-based electronic portal imaging device (a-Si EPID) under clinical conditions. EPID measurements were performed using one prototype and two commercial aSi detectors on two linear accelerators; one with 4 and 6 MV and the other with 8 and 18 MV x-ray beams. First, the EPID signal and ionisation chamber measurements in a mini-phantom were compared to determine the amount of build-up required for EPID dosimetry. Subsequently, EPID signal characteristics were studied as a function of dose per pulse, pulse repetition frequency (PRF) and total dose, as well as the effects of ghosting. There was an over-response of the EPID signal compared to the ionisation chamber of up to 18%, with no additional build-up layer over an air gap range of 10 to 60 cm. The addition of a 2.5 mm thick copper plate sufficiently reduced this over-response to within 1% at clinically relevant patient-detector air gaps (>40 cm). The response of the EPIDs varied by up to 8% over a large range of dose per pulse values, PRF values and number of monitor units. EPID response showed an under-response at shorter beam times due to ghosting effects, which depended on the number of exposure frames for a fixed frame acquisition rate. With an appropriate build-up layer and corrections for dose per pulse, PRF and ghosting, the variation in the a-Si EPID response can be reduced to well within ±1%.

Megavoltage image contrast with low-atomic number target materials and amorphous silicon electronic portal imagers

Low-atomic number (Z) targets have been shown to improve contrast in megavoltage (MV) images when using film–screen detection systems. This research aims to quantify the effect of low-Z targets on MV image contrast using an amorphous silicon electronic portal image detector (a-Si EPID) through both experimental measurement and Monte Carlo (MC) simulation. Experimental beams were produced with the linac running in the 6 MeV electron mode and with a 1.0 cm aluminum (Al, Z = 13) target replacing flattening filtration in the carousel, (6 MeV/Al). A 2100EX Varian linac equipped with an aS500 EPID was used with the QC3 MV phantom for the majority of contrast measurements. The BEAMnrc/EGSnrc MC package was used to build a model of the full imaging system including beam generation (linac head), the a-Si detector and the contrast phantom. The model accurately reproduces contrast measurements to within 2.5% for both the standard 6 MV therapy beam and the 6 MeV/Al beam. The contrast advantage of 6 MeV/Al over 6 MV, as quantified with the QC3 phantom, ranged from a factor increase of 1.6 ± 0.1 to 2.8 ± 0.2. Only a modest improvement in contrast was seen when the incident electron energy was reduced to 4 MeV (up to factor of 1.2 ± 0.1 over 6 MeV/Al) or with removal of the copper build-up layer in the detector, (up to factor of 1.2 ± 0.1 over 6 MeV/Al). Further decreasing the target Z, to beryllium (Be, Z = 4), at 4 MeV showed no significant improvement over 4 MeV/Al. Experimentally, the contrast advantage of 6 MeV/Al over 6 MV was found to decrease with increasing patient thickness, as can be expected due to selective attenuation of low-energy photons. At head and neck-like thicknesses, the low-Z advantage is a factor increase of 1.7 ± 0.1.

プリント基板におけるCuダイレクトバイアホールレーザ加工に関する研究 : シリカフィラー添加基板のオーバーハング抑制効果(機械要素,潤滑,設計,生産加工,生産システムなど)

In recent years, electric devices have rapidly advanced in high performance and miniaturization. As a result, electric circuits on Printed Wiring Boards (PWBs) are becoming high-density and its layers are increasing more and more. Therefore, micro-via drilling technology using a laser has become the dominant method for drilling blind via-holes (BVHs). Cu-direct laser drilling has attracted attention as a new method. However, there are few reports dealing with Cu-direct laser drilling of PWBs. Especially, when the copper and the resin with a different processing threshold are drilled at the same time, a defect of the overhang occurs on the drilled hole. However, the overhang generation mechanism has not been clear. Therefore, we investigated the overhang generation mechanism by observation of drilled hole section in detail. Moreover, we estimated the influence of thermal conductivity of the build-up layer on the overhang length using finite element method (FEM). As a result, it was shown that the overhang length becomes smaller with thermal conductivity of the build-up layer increasing. Therefore, we carried out an experiment with prototype PWBs silica filler mixed in the build-up layer. Using the prototype PWBs, it was shown that overhang could be reduced as shown in FEM analysis results.

Sci-Thurs PM: Delivery-09: Improving megavoltage portal image contrast with low atomic number target materials.

to investigate the impact of low atomic number (Z) targets and detector design on megavoltage (MV) portal image contrast. two experimental beams were generated by replacing flattening filtration of a 2100EX linac with beryllium (Be) and aluminum (Al) targets and using the linac in 6 MeV electron mode. A standard MV contrast phantom was used to quantify planar image contrast for the standard 6MV and the 6MeVAl beam, incident on an amorphous silicon (a-Si) detector. Contrast versus separation for 6MV and 6MeV/Al was quantified using a 1 cm bone/solid water slab within increasing thicknesses of solid water. The Monte Carlo BEAMnrc/DOXYZnrc package was used to model beam generation and detection. The beam/detector model was validated with comparison to measured open field profiles. Low-Z target spectra differ significantly from the standard 6MV spectrum with Be-target and Al-target peaks at ∼ 25keV and ∼50keV, respectively. Approximately 1/3rd of the photon population is below 60keV for the 4MeV/Be beam. Planar contrast is increased significantly over that of 6MV using low-Z targets, showing additional improvement with removal of the detector's copper build-up layer. Contrast decreases with increasing separation more rapidly for 6MeV/Al than for 6MV; however contrast for the former is superior over the full range of separation examined. Use of low-Z linac target materials improves MV image contrast. An additional advantage is realized by removing the copper layer from the a-Si detector. This research has been sponsored by Varian Medical Systems, Incorporated.

SU‐GG‐J‐106: Improved Planar and Megavoltage Cone‐Beam Imaging Using Low‐Z Linear Accelerator Targets

Purpose: to examine the effect of using low atomic number (Z) target materials on megavoltage portal and cone‐beam CT (CBCT) image quality. Method and materials: for experimental measurements, four low‐Z targets were installed in a linear accelerator carousel (Varian 2100EX) for the generation of experimental spectra for imaging. The targets were composed of beryllium or aluminum with thicknesses set to approximately 60% of the CSDA range of either 4 MeV or 6 MeV electrons. For CBCT acquisition, the beam and detector were fixed, and a rotation stage was controlled by software to acquire multiple angular projections of phantoms. To examine photon energy spectra and to provide a means for optimizing the imaging system, the beam generation and detector panel were modeled using BEAMnrc/DOSXYZ Monte Carlo package. For 6MV, the beam/detector model was validated by comparing experimental and MC‐generated images of open fields. Results: The modeled, experimental spectra demonstrate the recovery of photons below 150 keV. For the 4 MeV/Be beam, for example, approximately 1/3rd of photons have energies below 60 keV. MC models of planar imaging show significant improvement of image contrast compared to the standard 6MV beam, and suggest that i) of the four energy/target combinations studied, the 4 MeV/Be combination provides the greatest contrast improvement and ii) a modest additional increase in contrast is achieved by removing the copper buildup layer from the detector. Initial low‐Z target CBCT images show improved image contrast; full quantitative results will be presented. Conclusion: The use of megavoltage electron beams combined with low‐Z targets offers the potential for improved image quality, particularly in terms of image contrast. This approach may be promising for improved and highly‐integrated on‐board megavoltage imaging.Conflict of interest: This research has been sponsored by Varian Medical Systems, Incorporated.

Three-Dimensional Conduction Heat Transfer Model for Laser Cladding Process

Cladding is the process of depositing a superior built-up layer on a substrate by fusion. In the present study a three-dimensional conduction heat transfer model is developed and solved using the finite-volume method in a nonorthogonal grid system for a blown-powder laser cladding process. Comparisons with experimental data for deposition of copper powder on SS316 stainless steel show that the developed model can predict the geometry of the buildup layer above the substrate within an acceptable range of tolerance. The overall absorption of the CO2 laser radiation is in the range of 14–17%.

Optical and Structural Properties of Multi Deposition Film Derived SiO&lt;sub&gt;2&lt;/sub&gt;-TiO&lt;sub&gt;2&lt;/sub&gt; Systems by Sol-Gel Process

SiO2-TiO2 systems were extensively investigated in sol-gel process to fabricate passive optical planar waveguides, channel waveguides, interference filters and weather resistant optical memory discs. A high quality, crack free optical thick layer and low processing cost are key success factor for optical applications. Two formulated SiO2-TiO2 systems with 1% and 10% TiO2 were deposited on 20mm x 20mm Si-wafer using multi-spin coating process was investigated on refractive index (n), build-up layer until crack appeared on film. The structure analysis of multi spin was investigated using FTIR. The value of refractive index (n) and thickness of thin films (d) were taken every deposited layer using spectroscopic reflectance and surface morphology of crack thick film by FESEM. SiO2-TiO2 thin film appeared peak ~950cm-1 associated with the Si-O stretching vibrations of Si-OH and Si-O-Ti groups by multi spin coating processes. SiO2-TiO2 system with 10% TiO2 in siloxane structure was found capable on building thick layer up to 2.4 μm at 17 time cycles spins and heat treatments at 680 oC. The value of n was reduced with increasing of number of cycles and believes to form nanoporous zones between interfacial layers during hydrolysis and condensation process of each layer by multi spin coating process.

Adsorption of Amylase Enzyme on Ultrafiltration Membranes

A method to measure the static adsorption on membrane surfaces has been developed and described. The static adsorption of amylase-F has been measured on two different ultrafiltration membranes, both with a cutoff value of 10 kDa (a PES membrane and the ETNA10PP membrane, which is a surface-modified PVDF membrane). The adsorption follows the Langmuir adsorption theory. Thus, the static adsorption consists of monolayer coverage and is expressed both as a permeability drop and an adsorption resistance. From the adsorption isotherms, the maximum static permeability drops and the maximum static adsorption resistances are determined. The maximum static permeability drop for the hydrophobic PES membrane is 75%, and the maximum static adsorption resistance is 0.014 m2.h.bar/L. The maximum static permeability drop for the hydrophilic surface-modified PVDF membrane (ETNA10PP) is 23%, and the maximum static adsorption resistance is 0.0046 m2.h.bar/L. The difference in maximum static adsorption, by a factor of around 3, affects the performance during the filtration of a 5 g/L amylase-F solution at 2 bar. The two membranes behave very similarly during filtration with almost equal fluxes and retentions even though the initial water permeability of the PES membrane is around 3 times larger than the initial water permeability of the ETNA10PP membrane. This is mainly attributed to the larger maximum static adsorption of the PES membrane. The permeability drop during filtration exceeds the maximum static permeability drop, indicating that the buildup layer on the membranes during filtration exceeds monolayer coverage, which is also seen by the increase in fouling resistance during filtration. The accumulated layer on the membrane surface can be described as a continually increasing cake-layer thickness, which is independent of the membrane type. At higher concentrations of enzyme, concentration polarization effects cannot be neglected. Therefore, stagnant film theory and the osmotic pressure model can describe the relationship between flux and bulk concentration.