Buffering Scheme Research Articles

Data-dependent half-select free GSRAM cell with word line write-assist and built-in read buffer schemes for use in PUFs-based IoT devices

In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-Vth techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR2, which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.

Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inference

Recent advancements in large language models (LLMs) boasting billions of parameters have generated a significant demand for efficient deployment in inference workloads. While hardware accelerators for Transformer-based models have been extensively studied, the majority of existing approaches rely on temporal architectures that reuse hardware units for different network layers and operators. However, these methods often encounter challenges in achieving low latency due to considerable memory access overhead. This paper investigates the feasibility and potential of model-specific spatial acceleration for LLM inference on FPGAs. Our approach involves the specialization of distinct hardware units for specific operators or layers, facilitating direct communication between them through a dataflow architecture while minimizing off-chip memory accesses. We introduce a comprehensive analytical model for estimating the performance of a spatial LLM accelerator, taking into account the on-chip compute and memory resources available on an FPGA. This model can be extended to multi-FPGA settings for distributed inference. Through our analysis, we can identify the most effective parallelization and buffering schemes for the accelerator and, crucially, determine the scenarios in which FPGA-based spatial acceleration can outperform its GPU-based counterpart. To enable more productive implementations of an LLM model on FPGAs, we further provide a library of high-level synthesis (HLS) kernels that are composable and reusable. This library will be made available as open-source. To validate the effectiveness of both our analytical model and HLS library, we have implemented BERT and GPT2 on an AMD Xilinx Alveo U280 FPGA device. Experimental results demonstrate our approach can achieve up to 13.4 × speedup when compared to previous FPGA-based accelerators for the BERT model. For GPT generative inference, we attain a 2.2 × speedup compared to DFX, an FPGA overlay, in the prefill stage, while achieving a 1.9 × speedup and a 5.7 × improvement in energy efficiency compared to the NVIDIA A100 GPU in the decode stage.

A regularized lattice Boltzmann method based on the multi-layer grid using a buffer scheme

The regularized lattice Boltzmann method (RLBM) has the advantage of improving the accuracy of numerical simulations without increasing the computational overhead. The RLBM usually uses the standard Cartesian grid in numerical simulation. This paper introduces the multi-layer grid technique, the multi-layer grid has different resolutions, which is also more consistent with the physical laws of the flow field. Based on this, a multi-layer grid regularized lattice Boltzmann method (ML-RLBM) for solving complex flow problems is proposed. The proposed method performs local refinement of the grid on the standard Cartesian grid to achieve a multi-layer grid, which can reduce the computational overhead. In order to realize the local grid refinement easily, this paper adopts the center point format to store the multi-layer grid. The ML-RLBM designs a buffer scheme between different layers of grids, which realizes that only spatial interpolation is required at the interface of different layers of grids without temporal interpolation. The numerical results show that the ML-RLBM has excellent numerical accuracy and numerical stability, and it can effectively reduce the computational cost.

An Innovative Embedded Processor-Based Signal Phase Shifter Algorithm

Digital filtration is widely used today in many application fields, and with the increased use of low-cost embedded processors, it can be applied to vast areas. A drawback of digital filtration algorithms is the introduction of phase angle shifts in the filtered signals, thereby creating undesirable characteristics in many application fields. In this work, low-pass filters of finite impulse response and infinite impulse response types are designed with an innovative buffering scheme to delay a digitally low-passed signal by an angle ranging from 0° to 180° for real-time signals. The application of the filtration and buffering scheme on a cost-effective embedded processor with limited signal processing capabilities opens the horizons for its applicability in many signal processing fields. In assessing its practicality, the generated filtered output signal is correlated with the original signal (a low-passed version), revealing correlation values reaching 0.99 in certain instances. The novelty of the proposed approach enables its application to a broad-spectrum area of digital signal filtration.

Effects of COVID‐19 support measures on bank lending: Lessons from the release of countercyclical capital buffer and loan guarantee schemes in Hong Kong

AbstractBased on a panel of banks in Hong Kong, we found that banks with a relatively thin capital buffer and liquidity before the pandemic may constrain their post‐pandemic loan growth. We further found strong evidence that the release of countercyclical capital buffer (CCyB) requirements amid the pandemic mitigated the capital constraint to support continued provision of bank credit to the real economy, but mainly to non‐hard hit economic sectors. Nevertheless, the credit flow to hard‐hit economic sectors is found to be well supported by the SME Financing Guarantee Scheme.

Optimizing GPU-Based Graph Sampling and Random Walk for Efficiency and Scalability

Graph sampling and random walk algorithms are playing increasingly important roles today because they can significantly reduce graph size while preserving structural information, thus enabling computationally intensive tasks on large-scale graphs. Current frameworks designed for graph sampling and random walk tasks are generally not efficient in terms of memory requirement and throughput. Not to mention that some of them result in biased results. To solve the above problems, we introduce Skywalker+, a high-performance graph sampling and random walk framework on multiple GPUs supporting multiple algorithms. Skywalker+ makes four key contributions: First, it realizes highly paralleled alias method on GPUs. Second, it applies finely adjusted workload-balancing techniques and locality-aware execution modes to present a highly efficient execution engine. Third, it optimizes the GPU memory usage with efficient buffering and data compression schemes. Last, it scales to multi-GPU to further enhance the system throughput. Abundant experiments show that Skywalker+ exhibits significant advantage over the baselines both in performance and utility.

ML-Based Performance Modeling in SDN-Enabled Data Center Networks

Traffic optimization and smart buffering are fundamental to achieve both great application performance and resource efficiency in data centers with heterogeneous workloads, including incast and elephant traffics. However, general performance models providing insights on how various factors affect traffic performance metrics needed by these management functions are missing. For the special case of incast, the existing models are analytical ones, either tightly coupled with a particular protocol version or specific to certain empirical data. Motivated by this observation, this paper proposes an SDN-enabled machine-learning-based performance modeling approach in data center networks that leverages random forest predictions. Evaluations based on datasets constructed through intensive NS-3 simulations show that we can achieve accurate predictions of incast and elephant performance metrics based on various features. With this performance modeling capability, smart buffering schemes or traffic optimization algorithms could anticipate and efficiently optimize system parameters adjustment to achieve optimal performance continuously in data centers.

Enhancing the electron mobility in Si-doped (010) β-Ga2O3 films with low-temperature buffer layers

We demonstrate a new substrate cleaning and buffer growth scheme in β-Ga2O3 epitaxial thin films using metal–organic vapor phase epitaxy (MOVPE). For the channel structure, a low-temperature (LT, 600 °C) un-doped Ga2O3 buffer was grown, followed by a transition layer to a high-temperature (HT, 810 °C) Si-doped Ga2O3 channel layers without growth interruption. The (010) Ga2O3 Fe-doped substrate cleaning uses solvent cleaning, followed by additional hydrofluoric acid (49% in water) treatment for 30 min before the epilayer growth. This step is shown to compensate the parasitic Si channel at the epilayer–substrate interface that originates from the substrate polishing process or contamination from the ambient. From secondary ion mass spectroscopy (SIMS) analysis, the Si peak atomic density at the substrate interface is found to be several times lower than the Fe atomic density in the substrate—indicating full compensation. The elimination of the parasitic electron channel at the epi–substrate interface was also verified by electrical (capacitance–voltage profiling) measurements. In the LT-grown (600 °C) buffer layers, it is seen that the Fe forward decay tail from the substrate is very sharp, with a decay rate of ∼9 nm/dec. X-ray off-axis rocking curve ω-scans show very narrow full width at half maximum (FWHM) values, similar to the as-received substrates. These channels show record high electron mobility in the range of 196–85 cm2/V⋅s in unintentionally doped and Si-doped films in the doping range of 2 × 1016–1 × 1020 cm−3. Si delta-doped channels were also grown utilizing this substrate cleaning and the hybrid LT buffers. Record high electron Hall mobility of 110 cm2/V⋅s was measured for sheet charge density of 9.2 × 1012 cm−2. This substrate cleaning, combined with the LT buffer scheme, shows the potential of designing Si-doped β-Ga2O3 channels with exceptional transport properties for high-performance Ga2O3-based electron devices.

Buffer scheme for aero-performance deterioration caused by trains passing bilateral vertical noise barriers with crosswinds

Bilateral vertical noise barriers have been widely used along high-speed railway lines in coastal cities where typhoons are frequent. When a high-speed train (HST) enters (or exits) a noise barrier under strong crosswind conditions, its running safety will be more severely tested because of the instantaneous switching of aerodynamic environment. Installing a buffer structure at the end of the noise barrier is necessary to ensure the running safety of HSTs. In this study, two types of aerodynamic buffer structures (triangle and fence types) for the end of the noise barrier are proposed. The buffering effects of the two structures on the sudden change amplitude of the aerodynamic load of the carriage are compared by using an improved delayed detached eddy simulation method. The difference in the influence of the two buffer structures on the aerodynamic responses of the carriage is discussed by using a wind–train–bridge coupling dynamic response calculation method. The buffer mechanisms of the two structures are revealed in terms of the flow field. Results show that the buffering effect of fence type is superior triangle type, and the buffer length of 4 L is the most reasonable.

SwMPAS-A: Scaling MPAS-A to 39 Million Heterogeneous Cores on the New Generation Sunway Supercomputer

With the computing power of High-Performance Computing (HPC) systems having stepped into the exascale era, more complex problems can be solved with scientific applications on a large scale. However, due to the significant performance gap between computing nodes and storage subsystems, suboptimal design for the Input/Output (I/O) module will significantly impede the efficiency of scientific applications, especially for the ubiquitous atmosphere applications. Two-phase I/O implemented in N-to-1 mode creates a serious bottleneck that hinders the scalability for the Model for Prediction Across Scales-Atmosphere (MPAS-A) on the new generation Sunway supercomputer. To address the I/O problem, we apply a custom data reorganization method to enable N-to-M I/O mode to exploit the parallel file system's performance and limit the data transfer among MPI ranks to a restricted scope to alleviate communication overhead. Moreover, we have conducted several methods to accelerate the computations, including the redesign for tracer transport, a hybrid buffering scheme, and a three-level parallelization scheme, which allows MPAS-A to use all heterogeneous computing resources efficiently. Experimental results show admirable scalability and efficiency of our I/O method, which achieves speedups of 41× and 58.9× for input and output compared with the raw I/O method on 30,000 MPI ranks. By scaling MPAS-A to 39 million heterogeneous cores, we demonstrate the necessity of a well-constructed I/O module for a real-world atmosphere application. Speed tests show that our optimization methods obtain good results for computations, and MPAS-A achieves a speed of 0.82 Simulated Day per Hour (SDPH) and 0.76 parallel efficiency of strong scaling with 600,000 MPI ranks.

ВИСОКОЛІНІЙНІ БУФЕРИ НАПРУГИ ДЛЯ ВИСОКОПРОДУКТИВНИХ АЦП І ЦАП

The article analyzes the proposed methods of structural and functional organization of highly linear voltage buffers built according to two-stroke symmetrical structures. In the first method, it is assumed to increase the resistance of the current outputs. Thanks to this, it is possible to stabilize the collector-emitter junction voltage of the transistors of the output stages. In the second method, it is proposed to reduce the influence of the base current of the transistors of the output stages, which will reduce the linearity error. In the third method, it is proposed to increase the linearity without reducing the speed level, by stabilizing the collector-emitter voltages of the output stages. It is shown that the use of voltage stabilization of the collector-emitter transitions makes it possible to improve the circuit characteristics by 1÷2 orders of magnitude. Analytical dependencies describing the linearity errors of the cores of voltage buffers, which are built according to a two-stroke symmetrical structure, are derived. It is shown that the proposed approaches allow to reduce the errors of linearity and zero shift by an order of magnitude or more. To determine the components that affect the appearance of the error, an equivalent scheme for replacing the output of the voltage buffer core is considered. It was determined that the proposed methods of building voltage buffers have a common drawback, namely, low load capacity, which is determined by the output resistances of the circuits. An approach that allows increasing the load capacity of voltage buffers is considered. It is shown that it makes it possible to reduce the output resistance by 2÷3 orders of magnitude. In order to increase the load capacity and maintain the specified linearity of the voltage buffer scheme, it is proposed to supplement it with a two-stroke two-channel current amplifier. The use of the proposed methods and approaches for the construction of voltage buffers allows obtaining such devices that have the necessary characteristics and can be used as part of high-performance ADCs and DACs.

Toward Fast and Scalable Random Walks over Disk-Resident Graphs via Efficient I/O Management

Traditional graph systems mainly use the iteration-based model, which iteratively loads graph blocks into memory for analysis so as to reduce random I/Os. However, this iteration-based model limits the efficiency and scalability of running random walk, which is a fundamental technique to analyze large graphs. In this article, we first propose a state-aware I/O model to improve the I/O efficiency of running random walk, then we develop a block-centric indexing and buffering scheme for managing walk data, and leverage an asynchronous walk updating strategy to improve random walk efficiency. We implement an I/O-efficient graph system, GraphWalker , which is efficient to handle very large disk-resident graphs and also scalable to run tens of billions of random walks with only a single commodity machine. Experiments show that GraphWalker can achieve more than an order of magnitude speedup when compared with DrunkardMob, which is tailored for random walks based on the classical graph system GraphChi, as well as two state-of-the-art single-machine graph systems, Graphene and GraFSoft. Furthermore, when compared with the most recent distributed system KnightKing, GraphWalker still achieves comparable performance with only a single machine, thereby making it a more cost-effective alternative.

Implementation of a real‐time stereo vision algorithm on a cost‐effective heterogeneous multicore platform

SummaryStereo vision is a major computer vision technique commonly used for robotics applications. Existing software implementations of this technique on general‐purpose processors offer low time‐to‐market compared to other platforms. However, such implementations can hardly achieve real‐time and their cost is usually relatively high. These issues can be solved by embedded multicore platforms. In this article, we present a low‐cost, improved software implementation of a stereo matching algorithm in the correlation stage that combines a sparse rank transform with a combination of sum of absolute differences 1‐D and 2‐D box filtering algorithms. A circular buffer scheme is used to optimize memory usage during the rank computation stage. The system runs on a heterogeneous multicore platform (ODROID XU4). Through the extensive use of single instruction multiple data Neon intrinsics, the system can process images with a size of pixels and a disparity range of 20 pixels at a rate of 111 frames per second. The proposed system can be used in mobile robot platforms that require low power consumption while delivering real‐time performance.

RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection

Due to the so-called curse of dimensionality and increase in the size of databases, there is an ever-increasing demand for computing resources and memory bandwidth when performing the k-nearest neighbors (kNNs) algorithm, resulting in a slow-down to process large datasets. This work presents an OpenCL-based framework for accelerating the kNN algorithm on field-programmable gate arrays (FPGAs) benefiting from the random projection dimensionality reduction. The proposed RPkNN framework includes two compute modules implementing a throughput-optimized hardware architecture based on random projection and the kNN algorithm and a host program facilitating easy integration of the compute modules in the existing applications. RPkNN also utilizes a new buffering scheme tailored to random projection and the kNN algorithm. The proposed architecture enables parallel kNN computations with a single memory channel and takes advantage of the sparsity features of the input data to implement a highly optimized and parallel implementation of random projection. We employ a computation storage device (CSD) to directly access the high-dimensional data on non-volatile memory express (NVMe) solid state drive (SSD) and store and reuse the compressed and low-dimensional data on the FPGA dynamic random access memory (DRAM), hence eliminating data transfers to the host DRAM. We compare RPkNN implemented on the Samsung SmartSSD CSD with the kNN implementation of the scikit-learn library running on an Intel Xeon Gold 6154 CPU. The experimental results show that the proposed RPkNN solution achieves, on average, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$26\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$46\times $ </tex-math></inline-formula> higher performance across different dimensions per a single kNN computation for the SIFT1M and GIST1M databases, respectively. Finally, RPkNN is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> faster than the similar FPGA-based reference method.

The effects of COVID-19 support measures on bank lending: Lessons from the release of the Countercyclical Capital Buffer and Loan Guarantee Schemes in Hong Kong

The effects of COVID-19 support measures on bank lending: Lessons from the release of the Countercyclical Capital Buffer and Loan Guarantee Schemes in Hong Kong

Cooperative Buffering Schemes for Time-Shifted Live Streaming of Distributed Appliances

Distributed appliances connected to the Internet have provided various multimedia services. In particular, networked Personal Video Recorders (PVRs) can store broadcast TV programs in their storage devices or receive them from central servers, enabling people to watch the programs they want at any desired time. However, the conventional CDNs capable of supporting a large number of concurrent users have limitations in scalability because more servers are required in proportion to the increased users. To address this problem, we have developed a time-shifted live streaming system over P2P networks so that PVRs can share TV programs with each other. We propose cooperative buffering schemes to provide the streaming services for time-shifted periods even when the number of PVRs playing back at the periods is not sufficient; we do so by utilizing the idle resources of the PVRs playing at the live broadcast time. To determine which chunks to be buffered, they consider the degree of deficiency and proximity and the ratio of playback requests to chunk copies. Through extensive simulations, we show that our proposed buffering schemes can significantly extend the time-shifting hours and compare the performance of two buffering schemes in terms of playback continuity and startup delay.

Adaptive Multi-Grained Buffer Management for Database Systems

The traditional page-grained buffer manager in database systems has a low hit ratio when only a few tuples within a page are frequently accessed. To handle this issue, this paper proposes a new buffering scheme called the AMG-Buffer (Adaptive Multi-Grained Buffer). AMG-Buffer proposes to use two page buffers and a tuple buffer to organize the whole buffer. In this way, the AMG-Buffer can hold more hot tuples than a single page-grained buffer. Further, we notice that the tuple buffer may cause additional read I/Os when writing dirty tuples into disks. Thus, we introduce a new metric named clustering rate to quantify the hot-tuple rate in a page. The use of the tuple buffer is determined by the clustering rate, allowing the AMG-Buffer to adapt to different workloads. We conduct experiments on various workloads to compare the AMG-Buffer with several existing schemes, including LRU, LIRS, CFLRU, CFDC, and MG-Buffer. The results show that AMG-Buffer can significantly improve the hit ratio and reduce I/Os compared to its competitors. Moreover, the AMG-Buffer achieves the best performance on a dynamic workload as well as on a large data set, suggesting its adaptivity and scalability to changing workloads.

Coded-Caching Using Adaptive Transmission

In this letter, we study the effect of adaptive transmission on the performance of coded-caching based networks. Particularly, concentrating on the reduction of backhaul peak load during the high traffic periods, we develop adaptive rate and power allocation schemes maximizing the network successful transmission probability, which is defined as the average probability that the cache nodes decode their intended signals correctly. Moreover, we study the effect of different message decoding and buffering schemes on the system performance. As we show, the performance of coded-caching networks is considerably affected by rate/power allocation as well as the message decoding/buffering schemes.

Optimizing Superframe and Data Buffer to Achieve Maximum Throughput for 802.15.4-Based Energy Harvesting Wireless Sensor Networks

Energy harvesting wireless sensor networks (EH-WSNs) intend to support sustainable operations. It is important to design a high-throughput data delivery scheme that adapts to the fluctuation in harvested energy in the EH-WSN nodes. In this article, the optimal superframe and data buffer scheme (OSDBS) is investigated to improve the throughput of IEEE 802.15.4 beacon-enabled EH-WSNs. A stochastic model is developed for OSDBS, which leads to the characterization of network throughput and packet delay. The OSDBS achieves the maximum throughput through setting the optimal superframe and buffer sizes of the nodes, which are the solution of the formulated optimization problem that maximizes the network throughput with consideration of energy-harvesting rate and data arrival rate. The simulation results show the OSDBS significantly outperforms the existing schemes in terms of throughput.

A contribution to scheduling jobs submitted by finite-sources in computational clusters

Data science and data processing are very popular topics nowadays. Un- like a few years ago, everything is connected to data now and we have to handle these kinds of large data well. Therefore the distributed heterogeneous resources of networks e.g. the computational grid, have attracted great interest. It has become a challenge to schedule jobs in order to utilize the available resources effectively. The allocation of arriving jobs has a great impact on the efficiency and the energy consumption of the system. A generalized finite source model is presented in this paper. Our main goal is to build up models for the performance evaluation of scheduling computeintensive jobs with unknown service times in a computational cluster that consists of servers of different types. For this purpose we determine various performance measures for all combinations of three scheduling policies (two of them are the novelty of this paper: the MRT and the MRTHP policies) which can be used for assigning jobs to servers with three schemes for buffering arriving jobs. Furthermore, we investigate the effect of switching off idle servers on the energy consumption of the system under these combinations of scheduling policies and buffering schemes. Computational results obtained by simulation show that the choice of the scheduling policy and the buffering scheme plays an important role in ensuring the quality of service parameters such as the waiting time and the response time experienced in the case of arriving jobs. However, the energy consumption is only affected by the scheduling policy and the energy saving mode, while the buffering scheme does not have a significant impact.