Buffering Scheme Research Articles

A Sovereign Risk-Based Approach to Implementing Countercyclical Capital Buffer Schemes

Based on the macro-financial risk framework of Gray et al. (2006) that links the balance sheets of the financial sector and public sector together through government guarantees, we propose an indicator, sovereign distance-to-default (SDD), for implementing the countercyclical capital buffer schemes of Basel III. Using a sample of 29 European countries from 1975 to 2011, we find that SDD outperforms credit-to-GDP ratio, the primary indicator recommended by the Basel Committee for Banking Supervision. More specifically, SDD generates more reliable signals for the build-up of capital buffers three years prior to a crisis and the release of capital buffers in the same year that the crisis occurs. Our findings suggest that SDD can be used as a leading indicator for the build-up phase and an anchor for the release phase of the countercyclical capital buffer schemes.

A versatile digitally-graded buffer structure for metamorphic device applications

Exploring more effective buffer schemes for mitigating dislocation deficiencies is the key technology towards higher performance metamorphic devices. Here we demonstrate a versatile metamorphic grading structure consisting of 38-period alternated multilayers of In0.52Al0.48As and In0.82Al0.18As on InP substrate, thicknesses of which in each period were gradually varied in opposite directions from 48.7 and 1.3 nm to 1.3 and 48.7 nm, respectively, akin to a digital alloy. Both preferentially dislocation nucleation and blocking of threading dislocation transmission are observed near the In0.82Al0.18As/In0.52Al0.48As interfaces, which help relax the strain and lower the residual defect density. A 2.6 μm In0.83Ga0.17As pin photodetector is fabricated on this pseudo-substrate, attaining a low dark current density of 2.9 × 10−6 A cm−2 and a high detectivity of 1.8 × 1010 cmHz1/2W−1 at room temperature, comparable with the states of the art that on linearly-graded buffer layers. These results indicate such digitally-graded buffer structures are promising for enhancing performances of metamorphic devices, and can be easily generalized to other lattice-mismatched material systems.

An efficient implementation of 3D high-resolution imaging for large-scale seismic data with GPU/CPU heterogeneous parallel computing

De-absorption pre-stack time migration (QPSTM) compensates for the absorption and dispersion of seismic waves by introducing an effective Q parameter, thereby making it an effective tool for 3D, high-resolution imaging of seismic data. Although the optimal aperture obtained via stationary-phase migration reduces the computational cost of 3D QPSTM and yields 3D stationary-phase QPSTM, the associated computational efficiency is still the main problem in the processing of 3D, high-resolution images for real large-scale seismic data. In the current paper, we proposed a division method for large-scale, 3D seismic data to optimize the performance of stationary-phase QPSTM on clusters of graphics processing units (GPU). Then, we designed an imaging point parallel strategy to achieve an optimal parallel computing performance. Afterward, we adopted an asynchronous double buffering scheme for multi-stream to perform the GPU/CPU parallel computing. Moreover, several key optimization strategies of computation and storage based on the compute unified device architecture (CUDA) were adopted to accelerate the 3D stationary-phase QPSTM algorithm. Compared with the initial GPU code, the implementation of the key optimization steps, including thread optimization, shared memory optimization, register optimization and special function units (SFU), greatly improved the efficiency. A numerical example employing real large-scale, 3D seismic data showed that our scheme is nearly 80 times faster than the CPU-QPSTM algorithm. Our GPU/CPU heterogeneous parallel computing framework significant reduces the computational cost and facilitates 3D high-resolution imaging for large-scale seismic data.

Growth, structural, and electrical properties of germanium-on-silicon heterostructure by molecular beam epitaxy

The growth, morphological, and electrical properties of thin-film Ge grown by molecular beam epitaxy on Si using a two-step growth process were investigated. High-resolution x-ray diffraction analysis demonstrated ∼0.10% tensile-strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt. Micro-Raman spectroscopic analysis corroborated the strain-state of the Ge thin-film. Cross-sectional transmission electron microscopy revealed the formation of 90 ° Lomer dislocation network at Ge/Si heterointerface, suggesting the rapid and complete relaxation of Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphology with surface roughness < 2 nm. Temperature dependent Hall mobility measurements and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in Ge layer. Capacitance- and conductance-voltage measurements were performed to determine the effect of epilayer dislocation density on interfacial defect states (Dit) and their energy distribution. Finally, extracted Dit values were benchmarked against published Dit data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained were comparable with Ge MOS devices integrated on Si via alternative buffer schemes. This comprehensive study of directly-grown epitaxial Ge-on-Si provides a pathway for the development of Ge-based electronic devices on Si.

A Buffering and Switching Scheme for Admission Control in Cognitive Radio Networks

Cognitive radio users (i.e., secondary users) experience a lot of performance degradation due to the continuous appearance of primary users in the cognitive radio networks. To minimize the effect of this phenomenon, we propose a buffering and switching scheme for admission control to enhance the performance of the secondary users. In the proposed scheme, the secondary users are competing for the available channels (i.e., licensed and unlicensed) with two different kinds of users and utilizing different kinds of buffers to reduce the blocking probability for newly arriving users and dropping probability for ongoing connection. The system is modeled using a multi-dimensional continuous-time Markov chain, where the performance metrics are obtained. The numerical results are verified using a discrete event simulations.

Construction of Polynomial-Size Optical Priority Queues Using Linear Switches and Fiber Delay Lines

One of the main problems in all-optical packet switched networks is the buffering of packets. A popular solution for buffering packets is to use a set of fiber delay lines attached to a switch. A priority queue is one of the most general buffering schemes that allows the packet with the highest priority to depart the buffer on a departure request and dropping of the lowest priority packet if a new packet arrives when the buffer is full. We present a recursive algorithm for constructing optical priority queues of polynomial size from a switch with linear number of inputs/outputs and fiber delay lines. The best known lower bound allows the construction of a priority queue of size $2^{M}$ using a switch of size $M$ . However, the best known upper bound constructs a priority queue of size $M^{3}$ using a switch of size $M$ . We show that it is possible to construct a priority queue of size $O(M^{c})$ for a fixed constant $c$ using a switch of size $O(M)$ .

V-BAG: A virtual bandwidth aggregation scheme for Internet of Things data

In order to meet the two crucial requirements of Internet of Things (support of a large number of Internet of Things devices and low power consumption), this article proposes a novel and efficient virtual bandwidth aggregation scheme for Internet of Things data. Since many Internet of Things applications require reliable Internet of Things data transmission, a Transmission Control Protocol is chosen as a transport protocol in this article. The proposed scheme consists of three salient functions: packet scheduler, estimator, and ACK buffer. The packet scheduler provides an efficient heterogeneous link selection using the proposed scheduling algorithm. The estimator provides an accurate delay and bandwidth estimation of heterogeneous wireless links using network layer information. Finally, the ACK buffer substantially boosts the performance of the scheduler and estimator with a simple ACK buffering scheme. Our extensive analysis using a numerical method and simulation corroborates the outstanding performance of the proposed scheme. Because of the salient functions of the proposed scheme, it can provide maximum capacity for future Internet of Things data transmission.

An Adaptive Buffering Scheme for P2P Live and Time-Shifted Streaming

Recently, P2P streaming techniques have been a promising solution to a large-scale live streaming system because of their high scalability and low installation cost. In P2P live streaming systems, however, it is difficult to manage peers’ buffers effectively, because they can buffer only a limited amount of data around a live broadcasting time in the main memory and suffer from long playback lag due to the nature of P2P structures. In addition, the number of peers decreases rapidly as the playback position moves further from this time by performing time-shifted viewing. These situations widen the distribution of peers’ playback positions, thereby decreasing the degree of data duplication among peers. Moreover, it is hard to use each peer’s buffer as the caching area because the buffer area where the chunks that have already been played back are stored can be overwritten at any time by new chunks that will arrive soon. In this paper, we therefore propose a novel buffering scheme to significantly increase data duplication in buffering periods among peers in P2P live and time-shifted streaming systems. In our proposed scheme, the buffer ratio of each peer is adaptively adjusted according to its relative playback position in a group by increasing the ratio of the caching area in its buffer as its playback position moves earlier in time and increasing the ratio of the prefetching area as its playback position moves later. Through extensive simulations, we demonstrate that our proposed adaptive buffering scheme outperforms the conventional buffering technique considerably in terms of startup delay, average jitter ratio, and the ratio of necessary chunks in a buffermap.

A flash-aware buffering scheme with the on-the-fly redo for efficient data management in flash storage

Thanks to remarkably fast random reads and rapidly decreasing prices per bit, flash storage has been regarded as a promising alternative to traditional hard disk drives (HDDs). Although flash storage has many distinguished hardware features, it still suffers from the poor I/O performance in the case of update operations. Due to the absence of in-place updates, differently from HDDs, flash storage needs to modify data through out-of-place updates. For this reason, it is required to continuously renew the mapping information between a logical page address and its new physical address, invalidating its old physical address. When the invalidated pages swallow most of free space in flash storage, the actions of garbage reclamation are needed. Since the actions of garbage reclamation are very costly, it is crucial to reduce the number of update operations for the use of flash storage in enterprise-scale database systems. In this light, we propose a new buffering scheme that evicts dirty pages without writing them to storage, thereby reducing the amount of update operations considerably. That is, our buffering scheme enables the flushing-less evictions of dirty pages. To correctly read a page undergoing its flushing-less eviction, we propose a new on-the-fly redo mechanism that enables restoring the lost updates of the page in normal database processing. For fast execution of the on-the-fly redo, we maintain memory-resident log data of a reasonable size. To show the performance advantages of the proposed scheme, we performed extensive experiments based on the TPC-C benchmark, by running them on the open-sourced Berkeley DB equipped with/without our scheme. The results show that our scheme yields a much better performance by reducing the amount of page updates significantly.

Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects

We propose a low-voltage, low-current interconnect architecture using buffered/pipelined spin-torque (ST) sensors to optimize the overall delay and energy consumption. Conventional techniques for reducing energy consumption on long interconnects involve low voltage swings on interconnects or current-mode interconnects. However, such techniques require power-consuming voltage converters or trans-impedance amplifiers at the receivers. ST-sensor-based receivers have recently been introduced that can operate without analog components at the receiver. As a result, the energy consumption is lower compared to existing techniques. However, the delay can be relatively high in these networks for long Cu-lines since these methods do not accommodate conventional buffering schemes for delay minimization. Here, we propose the use of ST buffers in the line in addition to ST-sensing at the receiver. The buffers and sensors used in our design consist of a magnetic strip of two magnetic domains separated by a domain wall. The domain wall can be moved by a current flowing through an adjacent spin-Hall metal which leads to a change in the resistance of the receiver. This resistance change is easily sensed using simple CMOS components. With the introduction of buffering for ST-sensor interconnects, the proposed method can be highly efficient in optimizing the energy-delay performance for long, global on-chip or off-chip lines. Our simulation results indicate that for a 10 mm line in 45 nm CMOS technology, the energy consumption with ST-sensing is about 2 percent that of full-swing, and about 4 percent that of low-swing, CMOS interconnects. Moreover, the delay is much lower than low-swing, and comparable to full-swing, CMOS designs.

Social-based routing scheme for fixed-line VANET

Vehicle Ad hoc NETwork (VANET) routing is facing a lot of challenges, such as efficient and effective message forwarding in the distributed network, as well as exploring and exploiting the movement regularity among vehicles and the social ties among passengers. Oriented to the fixed-line VANET, we propose a social-based routing scheme to enable the efficient and effective message routing among passengers. In the proposed scheme, passengers are divided into different communities based on the Improved K-Clique community detection algorithm (IKC). For determining the forwarding and dropping order of messages, a Social-based Message Buffering scheme at vehicles (SMB) is devised with their closeness and contribution considered. A Bilateral Forwarder Determination method (BFD) is proposed to make the optimal message forwarding, including Intra-Community Forwarder Determination (ICFD) and intEr-Community Forwarder Determination (ECFD). Simulation results show that the proposed scheme has better message delivery ratio and lower network overhead than other existing ones.

Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation

The paper presented here offers a two stage amplifier where both stages are in class AB mode. The input stage makes use of a floating gate metal oxide semiconductor (FGMOS) transistor which enables this circuit to operate at lower voltage and also increases overall linearity. The frequency compensation is done using voltage buffer scheme. A super source follower (SSF) acts as voltage buffer and exploited here with a series capacitor. The function of SSF is to enhance phase margin (PM) and gain bandwidth product (GBW) of the amplifier. The small signal equivalent and mathematical analysis of circuit is also given. The performance of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18μm process parameters. The ac simulation results of amplifier show that GBW is 9MHz and power consumption is 0.5mW.

A − 137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter

This paper presents a hybrid supply modulator (SM) with a comprehensive analysis of receiver (RX) band noise in an envelope tracking power amplifier (ET-PA). The designed SM supports both ET mode and average power tracking (APT) mode depending on the PA output power level. In the APT mode, an integrated buck-boost (BB) converter with hysteretic control generates dc supply voltage and its average switching frequency ranges from 1 to 2 MHz. In the ET mode, the bandwidth of SM is determined by a linear amplifier, which has about 30 MHz of signal bandwidth. To improve the ET efficiency, an ac coupling capacitor, with an adaptive offset control, and scaled linear supply are used. The scaled linear supply is provided by the BB converter. To lower the output noise of the SM, a parallel class-AB output buffer and resonance frequency tuning schemes are applied in this paper. For long term evolution 10 MHz with quadrature phase shift keying modulation and 5.8 dB peak-to-average power ratio, the designed SM achieves 82% efficiency at 800 mW output power with a fixed 8 $\Omega $ resistor. Adapting the proposed SM to a PA, a 10 dB ET operation dynamic range is achieved while achieving a power added efficiency of 42.6% at 27 dBm PA output power. The measured SM output noise is −137 dBm/Hz at 95 MHz offset with the PA load, and the PA RX band noise is −124 dBm/Hz, which is dominated by the stand-alone PA itself. The chip is implemented with a 130 nm CMOS process and the die size is 5.0 mm2.

Modelling and dimensioning of a high-radix datacentre optical packet switch with recirculating optical buffers

Recently, high port-count optical packet switches, based on the Arrayed Waveguide Grating (AWG) device, have been proposed for providing the very high bandwidth and connectivity degree that will be required in future datacentre interconnection networks. A practical, cost-effective realisation of such a switch requires that over-subscription of the AWG cross-connect output ports be allowed, with the resulting packet contention being resolved using a packet buffering facility in the switch. In this paper, we propose an efficient AWG switch architecture of this type that uses a recirculating optical packet buffering scheme and we develop analytic modelling methods to estimate the switch packet blocking probability and packet buffering delay. The analytic model resolves internal traffic flows in the switch as Markov-modulated Poisson Processes (MMPP) and also allows modelling of offered load to the switch as a MMPP process. Taking this model of the switch, we first show its accuracy compared to discrete event simulations and then use it to develop a heuristic optimisation algorithm to dimension the switch hardware components, with the objective of minimising the operating cost by optimally dimensioning the main power consuming components, subject to constraints on the maximum contention probability and average and maximum propagation delays. The resulting optimised switch design demonstrates the proposed architecture to be a promising candidate for future high-port count datacentre switches.

Playout buffer and DRX aware scheduling scheme for video streaming over LTE system

In this study, a playout buffer and discontinuous reception (DRX) aware scheduling scheme (PBDAS) is proposed to improve the video streaming transmission over the long term evolution systems by considering the characteristics of both the DRX mechanism and the HTTP streaming. First, to reconcile the three mechanisms, the metric called remaining playout time (RPT) is proposed, which can be used to estimate the playout status of the clients. With the RPT, the scheduler can accurately differentiate the urgency among the clients. Then, a two level resource allocation schemes is proposed. In the scheduler, the upper level is responsible for determining the scheduling set, while the lower level will be in charge of allocating the resource to the user equipments (UEs) in the set. With the scheduling set, the priority of the UEs can be accurately distinguished. For different scheduling set, different forms of metrics are designed, with which both the efficiency of the radio resource and the playout continuity can be significantly improved. In addition, a playout buffer level estimation method is given to improve the feasibility of the implementation of PBDAS. By analysing the behaviour of the playout buffer, the buffer level can be estimated with the cumulative serving rate and the HTTP streaming information, which can be obtained in the eNodeB and from the quality of experience reports, respectively. The simulation results show that PBDAS can shorten the total interruption duration of the existing schemes by about 50% as well as keep the power consumption at a low level.

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Two-dimensional (2-D) convolution is a widely used operation in image processing and computer vision, characterized by intensive computation and frequent memory accesses. Previous efforts to improve the performance of field-programmable gate array (FPGA) convolvers focused on the design of buffering schemes and on minimizing the use of multipliers. A recently proposed recurrently decomposable (RD) filter design method can reduce the computational complexity of 2-D convolutions by splitting the convolution between an image and a large mask into a sequence of convolutions using several smaller masks. This brief explores how to efficiently implement RD-based 2-D convolvers using FPGA. Three FPGA architectures are proposed based on RD filters, each with a different buffering scheme. The conclusion is that RD-based architectures achieve higher area efficiency than other previously reported state-of-the-art methods, especially for larger convolution masks. An area efficiency metric is also suggested, which allows the most appropriate architecture to be selected.

Realization of Efficient High Throughput Buffering Policies for Network on Chip Router

The communication between processing elements is suffering challenges due to power, area and latency. Temporary flit storage during communication consumes the maximum power of the whole power consumption of the chip. The majority of current NoCs consume a high amount of power and area for router buffers only. Removing buffers and virtual channels (VCs) significantly simplifies router design and reduces the power dissipation by a considerable amount. The buffering scheme used in virtual channeling in a network- on-chip based router plays a significant role in determining the performance of the whole network-on- chip based mesh. Elastic buffer (EB) flow control is a simple control logic in the channels to use pipeline flip- flops (FFs) as storage locations. With the use of elastic buffers, input buffers are no longer required hence leading to a simplified router design. In this paper properties of buffers are studied with a test microarchitecture router for several packet injection rates given at an input port. The prime contribution of this article is the evaluation of various forms of the elastic buffers for throughput, FPGA resource utilization, average power consumed, and the maximum speed offered. The article also gives a comparison with some available buffering policies against throughput. The paper presents the synthesis and implementation on FPGA platforms. The work will help NoC designers in suitable simple router implementation for their FPGA design. The implementation targets Virtex5 FPGA and Stratix III device family. Index Terms—Network-on-chip, virtual channels, buffers.

Redundant Network Traffic Elimination with GPU Accelerated Rabin Fingerprinting

Recently, redundant network traffic elimination has attracted a lot of attention from both the academia and the industry. A core challenge and enabling technique in implementing redundancy elimination is to perform content-based chunking, which typically involves the computationally heavy Rabin fingerprinting algorithm. In this paper, we propose a GPU-based implementation of Rabin fingerprinting to address this issue. To maximize performance gains, a diverse set of optimization strategies, such as efficient buffer management, GPU memory hierarchy optimization, and balanced load distribution, is proposed by either exploiting the intrinsic hardware features or addressing domain-specific challenges. Extensive evaluations on both the overall and microscopic performance reveal the effectiveness of the GPU-accelerated Rabin fingerprinting algorithm, and we can achieve up to 40 Gpbs throughput on a GTX 780 card. The throughput shows 1.87 $\times$ speedup against the state-of-the-art using comparable hardware. In addition, although some optimization designs are specific for the problem, techniques proposed in this work including the indexed compact buffer scheme and approximate sorting would also be beneficial and applicable to other network applications leveraging GPU acceleration.

Analysis of finite-source cluster networks

Nowadays the distributed heterogeneous resources of networks, like the computational grid, start to have a greater part of interest so, the investigations of such systems are vital. Because of the more efficient utilisation of the resources, the job scheduling becomes more challenging for the system administrators. The allocation of the arriving jobs has a great impact on the efficiency and the energy consumption of the system. In this paper, we present a finite source generalized model for the performance evaluation of scheduling compute-intensive jobs based on the infinite model of Tien Van Do. The available computers are classified into three groups. This classification is based on two aspects: high performance priority (HP) and energy efficiency priority (EE). We investigate three schemes (separate queue, class queue and common queue) for buffering the jobs in a computational cluster that is built from Commercial Off-The-Shelf (COTS) servers. Our main interest is to calculate performance measures and energy consumption of the system using the different buffering schemes and classifications.

Network Coding with Buffer Scheme in Multicast for Broadband Wireless Network

Network Coding with Buffer Scheme in Multicast for Broadband Wireless Network