Buffered FET Logic Research Articles

Three-stage monolithic optical preamplifier on GaAs substrate

A three-stage GaAs monolithic transimpedance preamplifier for 155 Mbps data-rate optical receiver has been designed, fabricated and tested . Mesa/epitaxial technology of 1 μm gate length D-MESFET is employed for its implementation. The feedback resistor is realized using GaAs epitaxial layer. The buffered FET logic (BFL) approach is followed for the amplifier design. A close correlation between the design and measured device parameters is achieved with overall gain of 36 dB at 130 MHz. A clear eye diagram of the hybrid optical receiver using front-illuminated lnGaAs/lnP PIN photodetector is presented indicating its suitability for 155 Mbps optical receiver applications.

Improved voltage gain of transimpedance amplifier by AlGaAs/InGaAs doped-channel FET's

AlGaAs/InGaAs doped-channel FET's were investigated, and were utilized for transimpedance (TZ) amplifier circuits. Due to a high current density, a high gain linearity, and high gate breakdown and turn-on voltages of device characteristics, the AlGaAs/InGaAs doped-channel FET is shown to increase the noise margins and voltage gain in a buffered FET logic (BFL) inverter circuit, as compared with the circuit performance built by GaAs MESFET's. This amplifier also improves transimpedance gain, dynamic signal level, and the 3-dB frequency bandwidth. The transimpedance gain-bandwidth product (Z/sub T//spl middot/BW) is 17 GHz/spl middot/k/spl Omega/, which is much higher than in previous published reports.

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 /spl mu/m non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DPTL 4-b carry lookahead adder

Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1- mu m non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890*0.652 mm/sup 2/ (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers). >

Characteristics of GaAs buffered FET logic (BFL) MESFETs and inverters exposed to high-energy neutrons

A systematic investigation of the effects of high-energy neutrons on GaAs metal-semiconductor field-effect transistors (MESFETs) and buffered FET logic (BFL) gates has been carried out. Discrete transistors, inverters, and ring oscillators were characterized and modeled as a function of neutron fluence. Measurements were made of the threshold voltage shifts, the transconductance degradation, and saturation current degradation of GaAs depletion mode MESFETs, which comprise the BFL logic gates, irradiated with neutron fluences ranging from 5*10/sup 13/ n/cm/sup 2/ to 2*10/sup 15/ n/cm/sup 2/ (for particle energies above 10 keV). The threshold voltage was found to shift positively by 0.45 V, the transconductance decreased to 3%, and the saturation current to 1% of their unirradiated values at the highest neutron fluence (2*10/sup 15/ n/cm/sup 2/). The BFL inverter characteristics were measured and successfully simulated with SPICE using device parameters extracted from the neutron-damaged FETs. Ring oscillator measurements were made to determine the effects of high-energy neutrons on the frequency performance of BFL circuits. The ring oscillator frequency decreased to 9% of its unirradiated value at the highest neutron fluence. >

GaAs MESFET differential pass-transistor logic

Two GaAs MESFET implementations of differential pass-transistor logic (DPTL) are presented. The DPTL logic technique combines the area efficiencies and high operation speeds of ratioless pass-transistor circuits with the additional features of noise immunity and low power dissipation. Circuit structures are presented for both depletion (D)-mode and enhancement/depletion (E/D)-mode MESFET technologies, and are compared with buffered FET logic (BFL) and direct-coupled FET logic (DCFL), respectively. Experimental results are provided to verify the functionality and the performance features of both DPTL forms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Development and evaluation of a GaAs MMIC phase-locked loop chip set for space applications

GaAs monolithic microwave integrated circuit (MMIC) chips designed for a phase-locked loop frequency source to be used in space applications have been developed. The chip set includes a three-stage resistive feedback amplifier with 13-dB gain in a 275 MHz to 5.85 GHz bandwidth, a 2.0-GHz voltage-controlled oscillator, a 2.8-GHz digital prescaler, and a VHF/UHF digital phase/frequency discriminator. Both analog and buffered-FET logic digital circuits were fabricated on the same wafer. The MMIC process which was developed for this application comprises molecular beam epitaxial deposition of the active layer, proton isolation, submicron gates, thin film TaN resistor deposition, and silicon nitride passivation. The chip set was used successfully to implement a 2.0 GHz all-GaAs phase-locked loop. >

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2- mu m gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1- mu m gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Ultra-high-speed digital circuit performance in 0.2- mu m gate-length AlInAs/GaInAs HEMT technology

The fabrication of fifteen-stage ring oscillators and static flip-flop frequency dividers with 0.2- mu m gate-length AlInAs/GaInAs HEMT technology is described. The fabricated HEMT devices within the circuits demonstrated a g/sub m/ transconductance of 750 mS/mm and a full-channel current of 850 mA/mm. The measured cutoff frequency of the device is 120 GHz. The shortest gate delay measured for buffered-FET-logic (BFL) ring oscillators at 300 K was 9.3 ps at 66.7 mW/gate (fan-out=1); fan-out sensitivity was 1.5 ps per fanout. The shortest gate delay measured for capacitively enhanced logic (CEL) ring oscillators at 300 K was 6.0 ps at 23.8 mW/gate (fan-out=1) with a fan-out sensitivity of 2.7 ps per fan-out. The CEL gate delay reduced to less than 5.0 ps with 11.35-mW power dissipation when measured at 77 K. The highest operating frequency for the static dividers was 26.7 GHz at 73.1 mW and 300 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fully ECL-compatible GaAs standard-cell library

A standard cell library for MSI circuits is described. It is based on buffered FET logic (BFL) with 1- mu m gate-length MESFET transistors. It contains gates, buffers, master-slave flip-flops, and ECL interfaces and it has been optimized to operate over the military temperature range. It is fully compatible with ECL circuits (signal level and power supply). Typical propagation delay is 80 ps for an inverter (FI=FO=1) and power dissipation is 5 mW per BFL cell. A realistic printed circuit board for test and demonstration is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A GaAs 4-bit adder-accumulator circuit for direct digital synthesis

A GaAs depletion-mode MESFET integrated circuit which is implemented with buffered FET logic and contains 155 gates is described. The chip is composed of a 4-bit adder, a 4-bit register, and lookahead-carry logic capable of connecting up to four chips in a 16-bit parallel adder-accumulator circuit for direct digital synthesis of a sinewave. Fully functional chips have been fabricated by a GaAs foundry. Design rules were conservatively set to 1.5- mu m FET gate lengths. In synchronous operation without clock skew, a 16-bit four-chip configuration was breadboarded and operated at clock frequencies up to 200 MHz. Both a 4-bit one-chip breadboard and an 8-bit two-chip breadboard operated at clock frequencies up to 340 MHz. Chip power dissipation is approximately 500 mW including pad driver circuits. A next-generation pipelined adder-accumulator design based on the experience gained with this chip design is presented. For the LSI pipelined design with 1- mu m gate length, maximum clock speed is projected as 800 MHz to 1 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison of field-effect transistor logic families for a GaAs depletion-mode metal semiconductor field-effect transistor

Normally-on or depletion-mode field-effect transistors (MESFET) form the basis of the most mature and robust GaAs active-circuit technology. Because of the negative threshold voltage, depletion-mode metal semiconductor field-effect transistors (D-MEFSET) need level shifters to enable the output of one transistor to switch the input of the next. Buffered FET logic (BFL) is the most popular approach leading to gates that are fast and have good output-drive capability, but they occupy a lot of space and consume a lot of power. Capacitor – FET logic (CFL) has about one quarter of the power dissipation of BFL and occupies a similar area of GaAs. CFL is as fast as BFL, but the output-drive capability is inferior.The aim of the work described here is to develop a family of CFL gates that are at least as fast as BFL under all loading conditions while maintaining the power advantage of CFL. Bootstrapping the load increases the speed, but the output drive remains unsatisfactory. A super-buffered arrangement results in the lowest power and good output drive but with a slight reduction in speed compared to BFL. A combination of super buffering and load bootstrapping results in a design that meets all requirements. For example, a CFL gate with 12 mW dissipation gives a delay of 49 ps for a fan-out of unity and a loading factor of 13 ps per fan-out. This is compared with the BFL values of 60 ps with 12 ps per fan-out and 40 mW for a gate with comparable area and input capacitance.The super CFL gates have been used in the design of a 2.4 Gb∙s−1 4: 1 multiplexer, which has been successfully fabricated using a standard depletion-mode foundry process. The total power is approximately two thirds of that which would have been dissipated by a BFL realization.

An ECL-compatible GaAs MESFET 1-kbit static RAM

A fully ECL-compatible GaAs enhancement/depletion (E/D)-MESFET 1-kb static RAM was designed, fabricated, and tested. Direct-coupled FET logic is used for the memory array while buffered FET logic is utilized in the peripheral circuitry to provide an ECL 100 K interface. The memory cell area is 774 /spl mu/m/SUP 2/, and the chip size is 2.0/spl times/1.75 mm/SUP 2/. Fabrication of the 1-kb RAM involves a fully implanted two-threshold process with true double-level metal interconnection. A minimum access time of 1.3 ns has been obtained with a total power dissipation of 1.4 W (memory array power dissipation is only ~40 mW). The output voltage swing across a 50-/spl Omega/ load is 750 mV.

Performance of carry lookahead generator circuit fabricated with gallium arsenide

A high-performance 4-bit carry lookahead generator macrocell integrated circuit similar to the commercial 2902, a member of the 2900-family microprocessor chip set, was designed and built using direct-coupled FET logic (DCFL) and buffered FET logic (BFL) GaAs technologies. The following propagation delay times and power dissipations were measured: DCFL version -T/SUB pd/=1.55 ns, P=34 mW; BFL version-T/SUB pd/=1.10 ns, P=520 mW. In contrast, the commercially available bipolar 2902 has a propagation delay (room temperature typical) of 4.5 ns with an average power dissipation of 260 mW.

A gallium arsenide configurable cell array using buffered FET logic

A GaAs configurable cell array has been fabricated using 1-/spl mu/m gate MESFETs on 3-in GaAs substrates using a planar fabrication technique. Depletion-mode MESFETs configured in buffered FET logic structures were used to implement the logic cells. The cells are programmable for several logic functions and two different drive capabilities. Placement and routing software was developed. Cell configuration and array organization were adjusted to optimize the efficiency of the placing and routing software. Measured results on several cell configurations with various device sizes yielded speed-power products ranging from 162 fJ and 460 fJ. A 306-cell array (equivalent to approximately 430 NOR gates) occupying a chip area of 2.0/spl times/2.8 mm was fabricated. A 5/spl times/5 bit parallel multiplier implemented with this array showed a multiplication time of 6.5 ns and a power dissipation ranging from 337 to 722 mW, corresponding to a cell power of 1.30-2.79 mW/cell.

Design and fabrication of depletion GaAs LSI high-speed 32-bit adder

A GaAs LSI 32-bit adder implemented in BFL (buffered FET logic) gates has been designed and fabricated to demonstrate the feasibility of high-performance depletion GaAs LSI. Power dissipation reduction has been successfully achieved by reducing the number of level-shifting diodes to one, conforming with the FET threshold voltage (-0.5 V) and supply voltages (2 V, -1 V). Computer simulation was carried out with the interconnect parasitic capacitance included. In the IC, carry-look-ahead operation was utilized for realizing high-speed performance for 32-bit addition. The fabricated IC implementation required 420 gates, including 2100 FETs and 420 diodes, within a chip area of 4.6 mm/spl times/2.5 mm. High-speed performance was evaluated by packaging an IC chip. A maximum addition time of 2.9 ns with power dissipation of 1.2 W was obtained.

A GaAs low-power normally-on 4-bit ripple carry adder

The realization and performance of a low-power buffered FET logic (1p-BFL) 4 bit ripple carry adder is reported. Performance measurements indicate a critical path average propagation delay of 1.9 ns at a total power dissipation of 45 mW, output buffers included (27 mW without). This corresponds to an average propagation delay of 380 ps/gate (FI/FO=/SUP 5///SUB 3/), an average power consumption of 1.56 mW/gate, and a power-delay product of 0.6 pJ. Best speed performance biasing conditions yield a 1.25 ns critical path average propagation delay at a total power dissipation of 180 mW (180 mW excluding buffers), which corresponds to an average gate delay, power consumption and power-delay product of 250 ps, 6 mW, and 1.5 pJ, respectively. Standard cell layout techniques yield an average gate density of 200 gates/mm/SUP 2/, interconnection wiring included.

An MSI GaAs integrated circuit: 4 bit arithmetic and logic unit

A GaAs 4 bit arithmetic and logic unit (ALU) has been fabricated using a planar ion implantation technique with 2 /spl mu/m gate length FETs. The basic circuit is a buffered FET logic (BFL) circuit composed of normally on GaAs MESFETs and Schottky diodes. The active layers of the FETs and diodes are made by implanting Si into Cr-doped semi-insulating GaAs substrate. This ALU contains 629 FETs and 225 diodes within an area of 1.6/spl times/2.1 mm/SUP 2/. The ALU, capable of driving 50 /spl Omega/ transmission lines, is mounted on a 24 lead flat package. A delay time of 2.1 ns through the data path and a total power dissipation of 1.2 W with supply voltages of +5 V and -3 V have been obtained.