Gate Buffer Research Articles

Effect of a gate buffer layer on the performance of a 4H-SiC Schottky barrier field-effect transistor

A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer.

Optically Triggered Power Switch Based on 4H-SiC Vertical JFET

An optically controlled power switch based on 4H-SiC Trenched and Implanted Vertical JFETs (TIVJFET) was developed that comprises three parts: an LED light-source driver, light-triggered integrated gate buffer driver, and vertical high power normally-off switch. The light-triggered integrated gate buffer driver includes a photodiode and four stages of low voltage 4H-SiC TIVJFETs, which are hybrid integrated. Optically gated power switching was experimentally demonstrated with a maximum switching frequency of about 50 kHz, the system performance limiting factors were clearly identified and experimentally confirmed, and ways to substantially increase the switching frequency were shown. From calculations, based on realistically possible system parameters values, it could be seen that a maximum switching frequency around 1 MHz is theoretically possible with a proper choice of light source, detector, and buffer transistor parameters.

Shedding Physical Synthesis Area Bloat

Area bloat in physical synthesis not only increases power dissipation, but also creates congestion problems, forces designers to enlarge the die area, rerun the whole design flow, and postpone the design deadline. As a result, it is vital for physical synthesis tools to achieve timing closure and low power consumption with intelligent area control. The major sources of area increase in a typical physical synthesis flow are from buffer insertion and gate sizing, both of which have been discussed extensively in the last two decades, where the main focus is individual optimized algorithm. However, building a practical physical synthesis flow with buffering and gate sizing to achieve the best timing/area/runtime is rarely discussed in any previous literatures. In this paper, we present two simple yet efficient buffering and gate sizing techniques and achieve a physical synthesis flow with much smaller area bloat. Compared to a traditional timing-driven flow, our work achieves 12% logic area growth reduction, 5.8% total area reduction, 10.1% wirelength reduction, and 770 ps worst slack improvement on average on 20 industrial designs in 65 nm and 45 nm.

A Theoretical Study of the Performance of a Single-Electron Transistor Buffer

This paper introduces the ensemble Monte Carlo (EMC) method to study the time behavior of single-electron-based logic gates. The method is then applied to a buffer-inverter gate and the results are examined. An analytical model for time behavior at the low-temperature limit is then introduced and its results are compared with those of the EMC. Finally, a compact model for the delay-error behavior of the buffer gate is introduced.

ECO Timing Optimization Using Spare Cells and Technology Remapping

We introduce in this paper a new problem of post-mask engineering change order (ECO) timing optimization using spare-cell rewiring and present a two-phase framework for this problem. Spare-cell rewiring is a popular technique for incremental timing optimization and/or functional change after the placement stage. The spare-cell rewiring problem is very challenging because of its dynamic wiring cost nature for selecting a spare cell, while the existing related problems consider only static wiring cost: once a standard cell is placed, its physical location is fixed and so is its wiring cost. For the spare-cell rewiring problem, each rewiring could make some spare cells become ordinary standard cells and some standard cells become new spare cells simultaneously. As a result, the wiring cost becomes dynamic and further complicates the optimization process. For the addressed problem, we present a two-phase framework of 1) buffer insertion and gate sizing followed by 2) technology remapping. For Phase 1, we present a dynamic programming algorithm considering the dynamic cost, called dynamic cost programming, for the ECO timing optimization with spare cells. Without loss of solution optimality, we further present an effective pruning method by selecting spare cells only inside an essential bounding polygon to reduce the solution space. For those ECO timing paths that cannot be fixed during Phase 1, we apply technology remapping on the spare cells to restructure the circuit to fix the timing violations. The whole framework is integrated into a commercial design flow. Experimental results based on five industry benchmarks show that our method is very effective and efficient in fixing the timing violations of ECO paths.

N-channel operation of pentacene thin-film transistors with ultrathin polymer gate buffer layer

N-channel operation of pentacene thin-film transistors with ultrathin poly(methyl methacrylate) (PMMA) gate buffer layer and gold source–drain electrode was observed. We prepared pentacene thin-film transistors with an 8-nm thick PMMA buffer layer on SiO 2 gate insulators and obtained electron and hole field-effect mobilities of 5.3 × 10 −2 cm 2/(V s) and 0.21 cm 2/(V s), respectively, in a vacuum of 0.1 Pa. In spite of using gold electrodes with a high work function, the electron mobility was considerably improved in comparison with previous studies, because the ultrathin PMMA film could decrease electron traps on SiO 2 surfaces, and enhance the electron accumulation by applied gate voltages.

N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO 2 gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO 2 surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO 2 surface.

Controllable readout circuit for indium gallium arsenide photodiode array applications

This study presents a controllable integration time readout integrated circuit (ROIC) with a 32 by 32 indium gallium arsenide (InGaAs) detector array. This ROIC is designed for InGaAs photodiode (PD) array detectors to operate at low input current and is suitable for the focal plane array (FPA) in near infrared (NIR) field. The integration time of this ROIC can be controlled by an external clock pulse, and is adjustable from 0.5 µs to infinity by varying the light intensity. Moreover, the pre-stage of ROIC is based on the buffer gate modulation input (BGMI) architecture with differential structure and a double delta sampling (DDS) circuit, providing better sensitivity, a wider dynamic range, a higher injection efficiency and reduced noise. Further, because this ROIC is built into a sample-and-hold circuit in the unit cell, it can operate in the full frame snapshot mode. The proposed ROIC has 1024 pixels and a 30-µm pixel pitch. It is implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm Complementary Metal-Oxide-Semiconductor (CMOS) process with a 5-V power supply. The output swing is over 2.2 V. It has ±5% non-linearity, 91.559 mW chip power dissipation and a chip area of 1.628×2.341 mm2 without pads.

Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning

This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal energy-delay (E/D) tradeoffs via the buffer gate sizes and adding supply voltage as an extra tuning knob. In addition, a detailed discussion of the practically achievable tradeoff ranges via the gate size and especially supply voltage tuning is present. We have applied the methodology for the design and fine tuning of the run-time switchable buffers within the Level-1 (L1) embedded SRAMs (eSRAM), confirming that a very wide range in delay and energy reduction (up to 50%) can be achieved when compared to solely optimal speed eSRAM design using conventional high speed buffers.

P‐30: A Relation Between an a‐Si: H Integrated Buffer Transistor Resistance and Falling Time of Gate Output Signal

AbstractIn case of using an a‐Si:H integrated gate driver for TFT‐LCD [1–4], it's important to define gate falling time exactly. Because an a‐Si:H integrated gate driver might degrade with bad environment easily, which result in gate signal delay or decreasing output signal. In other words, a little degradation of a‐Si:H gate driver affects the quality of picture. If a little degradation of a‐Si:H gate driver under special circumstance is inevitable, it's necessary to make a gate driver has so sufficient margin time within one horizontal time that cannot be interfered with next data signal. So, it's necessary to understand what factors affect the a‐Si:H integrated gate output signal. Especially, we focused an a effect of buffer transistor resistance for gate output signal. In our study, with a test a‐Si:H integrated gate driver pattern and simple simulation process, a relation a‐Si:H integrated buffer transistor resistance and gate output signal is analyzed.

Improvements in the Device Characteristics of Polycrystalline Silicon Thin-Film Transistors on Stainless Steel by UV Treatment

A significant improvement in device performance was observed for polycrystalline Si thin-film transistors (poly-Si TFTs) on stainless steel foil subjected to UV treatment prior to the deposition of the buffer layer and gate dielectric film of . This is presumably due to the reduction of the trap-state density in the poly-Si film and at the gate dielectric/poly-Si interface caused by the removal of the organic contamination, which might be induced during the planarization of the rough stainless steel. An excellent subthreshold gate swing of , low threshold voltage of , and very low off-current of , as well as a high field-effect mobility of , were achieved for the p-channel poly-Si TFTs on stainless steel. Thus, it is concluded that poly-Si TFTs on stainless steel can be comparable to those on a conventional glass substrate in terms of their overall device performance, including , , and the off-current.

Orientation and growth behavior of CaHfO 3 thin films on non-oxide substrates

The growth behavior of CaHfO 3 on (001) Ni and Ge substrates was examined. CaHfO 3 is a perovskite insulator that is suitable for applications as a buffer layer or gate dielectric. The tendency for CaHfO 3 growth on both (001) Ni and (001) Ge substrates is to orient with the CaHfO 3 (200) + (121) planes parallel to the surface, which corresponds to the (110) orientation in the pseudo-cubic geometry. This differs from that of CaHfO 3 on perovskites, such as (001) LaAlO 3, where a pseudo-cube-on-cube orientation is observed.

Simultaneous switching noise analysis using application specific device modeling

In this paper, we introduce an application-specific device modeling methodology to develop simple device model that accurately tracks the actual device I-V characteristics in relevant but bounded operating regions. We have specifically used a simple MOSFET model to precisely analyze the switching noises generated on a chip due to simultaneous driving of chip output pads by bulky buffer gates. Previous works in analytical modeling of simultaneous switching noises employed long-channel and /spl alpha/-power law transistor models; however, these models led to complex circuit equations that on truncation caused poor matching between manual analysis and actual simulation results. Also, in order to retain the simplicity of manual analysis, previous researchers ignored the parasitic capacitances of the bonding pads. This paper demonstrates that by using a simple application-specific transistor model, circuit equations can be solved precisely without requiring any gross approximations or model truncations, even when the inductance effects of bonding wires are simultaneously considered along with parasitic capacitances of the output pads. The analytical results derived in this paper tally with HSPICE simulation values within 3% deviations.

Silicon carbide distributed buffer gate turn-offthyristorstructure for blocking high voltages

Silicon carbide gate turn-off thyristor simulations indicate that including within the drift region an n-type layer, doped 5 × 1016 cm-3 and located 3 µm below the top of the drift region, improves the forward blocking state electrostatic field profile. This structure, with a 15 µm total drift region thickness and no other field termination, blocks 2211 V, against 757 V if the n-type buffer layer is left out.

Performance optimization by interacting netlist transformations and placement

Performance optimization has become one of the most important problems at all design stages of today's highly integrated circuits. During logic synthesis performance optimization is guided by only rough net delay models. Therefore, net delays cannot be optimized effectively during logic synthesis. As device dimensions are shrinking in deep submicron designs, net delays tend to dominate performance. Consequently, the netlist generated during logic synthesis is suboptimal as only rough approximations for the most dominant part of the path delays are available. In this paper, we present a placement approach that exploits the optimization potential of netlist transformations during placement. As netlist transformations are integrated into the placement process, they can be guided by more accurate net delay models. In contrast to previous approaches that apply netlist transformations during placement, our approach is not restricted to local transformations like buffer insertion and gate resizing, but exploits global dependencies between the signals in a circuit. On the average, the maximum path delay is reduced by 11% compared to the initial performance-driven placement of the original netlist. Furthermore, the experiments show that applying the same netlist transformation procedure before placement yields no improvement as net delays cannot be considered due to missing layout information.

Performance evaluation of adiabatic gates

In this paper, buffer and NAND-NOR adiabatic gates are compared to a gate designed with the traditional complementary metal-oxide-semiconductor (CMOS) approach. The comparison is carried out assuming both an assigned power supply and by setting its value in such a way as to minimize power consumption. General relationships, which are independent of process parameters, as well as being simple enough to be used in a pencil-and-paper evaluation, are calculated. The analysis is developed id detail for the fully adiabatic gates and extended to include partially adiabatic circuits such as 2N-2P and 2N-2N2P. The analytical results are validated by SPICE simulations using 0.8-/spl mu/m CMOS technology. The analysis shows that with the technology considered and a fan-out of three, the adiabatic buffer is advantageous at power clock rise times higher than 3 ns and 23 ns for the nonoptimized and the optimized design, respectively, assuming a 100-fF load capacitance. These rise times increase to 22 ns and 384 ns for the NAND-NOR gate. Moreover, all the minimum rise times increase linearly when the fan-out of the gate is increased.

Efficient algorithm for glitch power reduction

An efficient algorithm is proposed for reducing glitch power dissipation in CMOS logic circuits. The proposed algorithm takes a path balancing approach that is achieved using gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches but also the effective circuit capacitance. After gate sizing, buffers are inserted into the remaining unbalanced paths which have not been subjected to gate sizing. ILP has been employed to determine the location of inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5% of glitches are reduced on average.

Numerical simulation for digital applications of a coupled-SQUID gate with d.c.-biasing

We present some numerical simulation results for a non-latching Josephson gate which is referred as a coupled-superconducting quantum interference device (SQUID) (C-SQUID) gate. TheC-SQUID gate can perform several logic functions by tuning the bias current to the single-junction-SQUID input-stage. The encoder and the decoder composed of C-SQUID BUFFER and NOR gates are successfully simulated. A modified C-SQUID gate which utilizes kinetic inductance of Josephson junctions is also presented.

A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic

This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimization an update to the selection of buffered gates is made. In this way, high drive capability buffered (i.e., BiCMOS) gates with sufficiently low fan-out are identified and replaced with a lower power unbuffered (i.e., CMOS) version. As well, the optimality of the final design is assessed based on a lower-bound delay value that is calculated. Experimental results have confirmed the efficiency and utility of the proposed method. In 8-b adder or 8/spl times/8 b multiplier networks, just two iterations are sufficient to achieve a delay that is at worst within 0.6% of its final optimized value and at worst within 10% of the lower-bound value. In the design of BiCMOS networks, it is seen that a speed advantage (at equivalent power) can be systematically achieved by using a mix of CMOS and BiCMOS gates versus using all CMOS or all BiCMOS gates and that this advantage increases with the tightness of the power constraint and with load capacitance.

A unified theory for mixed CMOS/BiCMOS buffer optimization

A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS/BiCMOS gate delay is linearly dependent on fan-out f, that is the delay can be expressed as Af+B, where A and B are coefficients. The optimum fan-out f/sub OPT/ is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS/CMOS gate types such as NANDs and NORs in a unified framework. The existence of spurious capacitance is shown to increase the size of all transistors compared with the case without the spurious capacitance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>