Abstract
This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal energy-delay (E/D) tradeoffs via the buffer gate sizes and adding supply voltage as an extra tuning knob. In addition, a detailed discussion of the practically achievable tradeoff ranges via the gate size and especially supply voltage tuning is present. We have applied the methodology for the design and fine tuning of the run-time switchable buffers within the Level-1 (L1) embedded SRAMs (eSRAM), confirming that a very wide range in delay and energy reduction (up to 50%) can be achieved when compared to solely optimal speed eSRAM design using conventional high speed buffers.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
