Gate Buffer Research Articles

Rewiring native post-transcriptional global regulators to achieve designer, multi-layered genetic circuits

As synthetic biology expands, creating “drag-and-drop” regulatory tools that can achieve diverse regulatory outcomes are paramount. Herein, we develop a approach for engineering complex post-transcriptional control by rewiring the Carbon Storage Regulatory (Csr) Network of Escherichia coli. We co-opt native interactions of the Csr Network to establish post-transcriptional logic gates and achieve complex bacterial regulation. First, we rationally engineer RNA-protein interactions to create a genetic toolbox of 12 BUFFER Gates that achieves a 15-fold range of expression. Subsequently, we develop a Csr-regulated NOT Gate by integrating a cognate 5’ UTR that is natively Csr-activated into our platform. We then deploy the BUFFER and NOT gates to build a bi-directional regulator, two input Boolean Logic gates OR, NOR, AND and NAND and a pulse-generating circuit. Last, we port our Csr-regulated BUFFER Gate into three industrially relevant bacteria simply by leveraging the conserved Csr Network in each species.

14‐1: A Study on Flexibility Improvement of AMOLED Back Plane and Mask Reduction Process Architecture Using Photo‐sensitive Organic Insulation Films

In this work, the method of patterning inter‐layer deposition (ILD) and passivation layer (PVX) of the AMOLED back plane structure with an organic film was studied. By replacing the inorganic film of SiNx + SiO2 with an organic film Poly‐imide, back plane suitable for flexible AMOLED was secured. It was possible to secure equivalent TFT transfer characteristics of device compared to inorganic inter layer structure by applying low‐temperature buffer and 2nd gate insulator SiNx to the organic inter layer TFT device. Also, VIA + passivation layer 2 mask photo process was replaced with 1 mask photo process using a VIA Half‐tone mask. Both processes were able to secure a process architecture that can be applied to flexible and rollable displays in the future by using photo‐sensitive organic insulation films.

AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL

Gate sizing and buffer insertion for timing optimization are performed extensively in electronic design automation (EDA) flows. Both of them aim to adjust the upstream and downstream capacitances of gates/buffers to minimize delay. However, most of existing work focuses on gate sizing or buffer insertion independently. This paper proposes a learning-based timing optimization framework, AiTO, that combines reinforcement learning with graph neural network, to perform simultaneously gate sizing and buffer insertion. We model buffer insertion as a special gate sizing by determining possible buffer locations in advance and treating the buffer insertion and gate sizing as an RL process. Experimental results on 10 real designs (28-nm and 110-nm) show that, AiTO can achieve better worst negative slack (WNS) optimization results than OpenROAD while being able to improve the results of the commercial tool, Innovus, to some extent. Moreover, ablation studies demonstrate the benefits of performing simultaneous gate sizing and buffer insertion for timing optimization.

Single-End Half-Select Free Static RAM Cell Based on BWG CNFET Tri-value Buffer Gate Applicable in Highly Efficient IoT Platforms

Single-End Half-Select Free Static RAM Cell Based on BWG CNFET Tri-value Buffer Gate Applicable in Highly Efficient IoT Platforms

Construction of intelligent interfaces based on stimulus-responsive hydrogels and ligand-free gold nanoparticles for electrocatalysis of isoquercitrin

In recent years, researchers have taken a keen interest in intelligent electrochemical interfaces. Nevertheless, incorporating multiple stimuli-responsive properties while ensuring a significant electrochemical response remains an interesting question. In this work, ligand-free gold nanoclusters grown on carbon nitride supports (AuNCs@N-C) were loaded on pyrolytic graphite (PG) electrode by layer-by-layer (LbL) method to obtain the {AuNCs@N-C}3 inner layers with good catalytic effect on isoquercitrin (IQ, 3-(β-d-Glucopyranosyloxy)-3′,4′,5,7-tetrahydroxyflavone). Then, the semi-penetrating stimuli-responsive hydrogel poly(N-isopropyl acrylamide)-poly(acrylic acid) (PNIPAM-PAA) was modified on the catalytic layer surface by drop-coating method. As a result, we obtained reversible electrochemical responses triggered by changes in temperature, sodium sulfate concentration, and pH. A new type of logic gate has been created by combining the difference in peak current during the stimulus response with the change in potential corresponding to the peak current. A 3-input/3-output tri-state buffer gate and a 1-to-4 demultiplexer have been designed through careful simplification, offering a fresh approach to building electrochemical pharmaceutical logic gates.

Bismuth sulfide based resistive switching device as the key to advanced logic gate fabrication

A memristor is a two-terminal electrical component with the scope of future computing applications and analog electronics. In this report, bismuth sulfide decorated one-dimensional carbon nitride nanotube was synthesized and characterized with various analytical techniques. The electrical property of the synthesized material was measured using a two-terminal metal–insulator–metal type of device that exhibited the resistive switching characteristics with the ON to OFF ratio of 2 × 103. The electron transport mechanism of the device was followed by Schottky emission and Poole–Frenkel emission for a low conductance state and Ohmic conduction behavior at the high conductance state. A decrease in the trap depth was identified in the simulation study with increasing applied potential and that supported the proposed mechanism. Read endurance and retention behavior of the device are stable in nature, supported by the statistical analysis. Furthermore, a hybrid logic gate was designed using two identical memristors, one CMOS inverter, one resistor, one voltage divider, and a buffer gate. The designed logic gate exhibited stable nand and nor gate operation based on the control signal.

Analysis and Stabilization of Signal Reflections in Gate-to-Gate Connections for AQFP Circuits

Signal integrity of transmitted data is critical for achieving highly dense, large-scale superconductor circuits. Transmission line effects, such as signal reflections, are investigated and concepts from microwave circuit theory and conventional digital logic circuits are applied to AQFP circuits. The lossless transmission line model is used for interconnection modelling. The frequency content and timing characteristics of data signals are used to analytically predict a maximum propagation delay of 6.1 ps before failure due to reflections. This coincides well with our own results, and with those obtained in a separate study using simulation techniques. The investigation then extends towards the design of an impedance matching network with the aim of reducing reflections. The input impedance of a standard buffer gate is derived, and then matched to an 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> transmission line. The proposed impedance matching network maintains data signal integrity up to 3 millimetres. Energy analysis of the matching network is also performed and a 36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> increase in length for similar energy consumption is achieved over alternative solutions.

A 60-GHz Variable-Gain Phase Shifter With an Active RL Poly-Phase Filter

A 60-GHz variable-gain phase shifter consisting of an active I/Q generator and Gilbert-cell-based summing amplifier fabricated in a 65-nm bulk CMOS process is presented here. The proposed I/Q signal generator is implemented by inserting an RL poly-phase filter into the interstage node of a cascode amplifier, which provides good interstage matching and results in a finite gain in the I/Q generator. It also provides good isolation characteristics between the I/Q generator and the subsequent vector-summing amplifier due to the common gate buffer stages. Therefore, it minimizes the rms gain and phase errors of the phase shifter by maintaining accurate I/Q signals regardless of the input impedance of the vector-summing amplifier, which varies with the gain and phase states. The vector-summing amplifier is operated by a current-steering digital to analog converter (DAC) to keep the total dc current constant regardless of the gain and phase states, which makes the output return loss constant. The DAC makes the vector-summing amplifier generate an arbitrary vector by determining the sizes of the I and Q vectors, and the double pole, double throw (DPDT) switch determines the quadrants. The rms gain and phase errors of the proposed variable-gain phase shifter show the values of 0.13 dB and 0.36°, respectively, at 60 GHz with 4-bit gain control in a 20-dB dynamic range and 5-bit phase control at 360°. In the 3-dB frequency range of 56.8–64.1 GHz, the rms gain and phase error outcomes are 0.26 dB and 1.44°, respectively. The chip area and overall power consumption are measured and found to be 0.55 mm2 and 14.52 mW, respectively.

Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates

Superconductive single-flux-quantum (SFQ) circuits operate with very high clock frequency and its timing design is a difficult task. In circuit design, static timing analysis (STA) is a key process for evaluating and verifying the timing of a circuit design. Conventional timing analysis for SFQ circuits focuses on circuits composed of clocked gates and splitters; however, practical SFQ circuits are composed of various gates, i.e., not only clocked gates but also other gates, such as nondestructive read-out, confluence buffer, and clockless logic gates. In this article, to express timing constraints of both clocked gate cells and other cells, we define timing requirements of cells as minimum and maximum acceptable intervals on ordered pairs of input pins. Via these, we express timing constraints of cells in an SFQ circuit design. Furthermore, to eliminate unnecessary pessimism during variation-aware timing analysis, we propose a method of common path pessimism removal (CPPR) for SFQ circuits composed of various cells. We implement an STA tool using the defined timing constraints and the CPPR method. The experimental results show that our STA tool verifies the timing of SFQ circuits composed of various cells.

On the Channel Hot-Electron’s Interaction With C-Doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances. Besides field dependence, the critical voltage was found to be carrier energy dependent by comparing the performance of devices subjected to semi- ON-state stress with devices under OFF-state stress. Experimentation on HEMTs with different buffer carbon doping variations revealed the degradation phenomenon to be a function of carbon doping in the GaN buffer. Furthermore, detailed electric field and electron temperature analysis revealed the drain edge to be a hot spot in accelerating interaction of hot electrons with traps in the GaN buffer leading to gate current degradation. A mechanism based on hot electron–buffer trap interaction-induced thermoelastic stress buildup and subsequent defect formation in the GaN buffer is proposed to explain the observed performance degradations. Observations such as a significant rise in channel temperature and accumulation of mechanical stress in the GaN buffer validate the proposed mechanism. Finally, the processes responsible for degradation lead to catastrophic failure of the device for longer stress times by the formation of cracks and pits in the GaN buffer, as validated by the postfailure field emission scanning electron microscopy (FESEM) analysis.

CNTFET-based design of ternary logic gates with interchangeable standard positive and negative ternary output

This paper presents a novel CNTFET based design of ternary logics gates where all three ternary logics including standard, positive and negative ternary logic (ST, PT and NT) outputs for each gate are obtained from one structure and are interchangeable through some control inputs. Ternary logic overpowers the conventional binary logic in simplicity and energy efficiency as it reduces number of interconnects and chip area. In this paper design of ternary inverter, buffer, NAND, AND, NOR, OR, XOR and XNOR gates are presented where a unique feature of conversion between ST, PT, NT logic through a single output is being introduced. Besides a single logic gate is designed for a particular logic function and its complement combining both ternary and binary logic gate design technique. The proposed designs utilize the unique property of CNTFET, such as assigning the required threshold voltage value of the FET by changing the diameter of the carbon nanotube (CNT) through its chiral vector values which is very useful in designing multiple- valued logic (here ternary logic). The proposed circuits are simulated using Synopsys HSPICE with 32 nm CNTFET model provided by Stanford University and in each case average power values and propagation delays are duly noted. The effects of variation in some process parameters like channel length, dielectric oxide thickness and number of carbon nanotubes also have been discussed.

Spatial Association characteristics of facilities around scenic spots considering distance and orientation: A case study of 3A and above scenic spots in Beijing

In the urban tourism and service industry, the POI data with coordinate and attribute information of the major map platforms constitute one of the important data sources of the urban tourism and service industry. In this paper, the spatial data transaction database under four distances was established based on the gate buffer of 3A and above scenic spots in Beijing. The Apriori algorithm was used to calculate the lifting degree to obtain the distance for mining the best association features of 3A, 4A and 5A scenic spots, and then the association features of the three scenic spots in different directions were analysed.

A Bendable Biofuel Cell-Based Fully Integrated Biomedical Nanodevice for Point-of-Care Diagnosis of Scurvy.

Fully integrated nanodevices that allow the complete functional implementation without an external accessory or equipment are deemed to be one of the most ideal and ultimate goals for modern nanodevice design and construction. In this work, we demonstrate the first example of a bendable biofuel cell (BFC)-based fully integrated biomedical nanodevice with simple, palm-sized, easy-to-carry, pump-free, cost-saving, and easy-to-use features for the point-of-care (POC) diagnosis of scurvy from a single drop of untreated human serum (down to 0.2 μL) by integrating a bendable and disposable vitamin C/air microfluidic BFC (micro-BFC) (named iezCard) for self-powered vitamin C biosensing with a custom mini digital LED voltmeter (named iezBox) for signal processing and transmission, along with a ″built-in″ biocomputing BUFFER gate for intelligent diagnosis. Under the simplicity- and practicability-oriented idea, a cost-effective strategy (e.g., biomass-derived hierarchical micro-mesoporous carbon aerogels, screen-printed technique, a single piece of Kimwipes paper, LED display, and universal components) was implemented for nanodevice design rather than any top-end or pricey method (e.g., photolithography/electron-beam evaporation, peristaltic pump, wireless system, and 3D printing technique), which enormously reduces the cost of feedstock down to ∼USD 2.55 per integrated kit including a disposal iezCard (∼USD 0.08 per test) and a reusable iezBox (∼USD 2.47 for large-scale tests). These distinctive and attractive features allow such a fully integrated biomedical nanodevice to fully satisfy the basic requirements for POC diagnosis of scurvy from a single drop of raw human serum and make it particularly appropriate for resource-poor settings, where there is a lack of medical facilities, funds, and qualified personnel.

Energy Efficient Adiabatic Logic Circuit for Improve Security in DPA Resistant RFID

A Differential Power Analysis (DPA) attack is an exploit which overcomes the hardware and software security by analyzing the correlation between electricity usage of a chip in a device and the encryption key. These attacks are non-invasive, leading an intruder to crack a system without leaving any trace. CMOS Technology is prone to DPA attack because of higher power dissipation. A DPA resistant adiabatic technique has been analyzed which has lower power dissipation when compared to the CMOS technology. The conventional Positive Feedback Adiabatic Logic (PFAL) suffers from certain non-adiabatic energy loss. Hence, Energy Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) is proposed which reduces the non-uniform power consumption, preventing information leakage thus securing the system from DPA attacks. Thus the proposed EE-SPFAL is used to design logical circuits such as buffer, OR-XNOR and AND-NAND gate. It is proved that the information leakage in the form of current consumption takes place in PFAL buffer whereas current consumption traces in EE-SPFAL circuits are uniform, depicting the ability of the proposed logic family to resist DPA attack. The simulation was done using Cadence virtuoso 180 nm technologies.

Wide-range energy-efficient buffer-based voltage level-up converters for multi-supply voltage systems

The voltage level converters (LCs) are required to attain optimized power consumption by interfacing two or more supply voltage domains in Systems-on-Chip (SoC) applications. The voltage level-up conversion can be easily and effectively achieved by the use of buffer structures. Hence this article proposes two buffer-based LCs, namely transmission gate buffer level converter (TGBLC) and stacked PMOS buffer level converter (SPBLC), based on voltage stepping technique. The energy-efficient transmission gate (TG) and stacked PMOS (SP) structures are proposed to define voltage steps in the buffer and ensure a wider voltage conversion range with high speed. The LCs are implemented in 0.18 $$\mu $$ m technology and their performance metrics are verified using a Spectre circuit simulator. The simulation results show that TGBLC and SPBLC can convert a low input voltage of 600 and 550 mV to 1.8 V, respectively. For the target input voltage of 0.8 V with frequency of 1 MHz, the TGBLC and SPBLC exhibit an improved delay of 7.3 and 7.1 ns with an energy consumption of 9.66 and 6.66 pJ per transition, respectively. It is noted from the experimental results that the proposed LCs are suitable for applications where simplicity and energy efficiency/low power with a wider conversion range is preferred.

Tuning Extracellular Electron Transfer by Shewanella oneidensis Using Transcriptional Logic Gates

Extracellular electron transfer (EET) pathways, such as those in the bacterium Shewanella oneidensis, interface cellular metabolism with a variety of redox-driven applications. However, designer control over EET flux in S. oneidensis has proven challenging because a functional understanding of its EET pathway proteins and their effect on engineering parametrizations (e.g., response curves, dynamic range) is generally lacking. To address this, we systematically altered transcription and translation of single genes encoding parts of the primary EET pathway of S. oneidensis, CymA/MtrCAB, and examined how expression differences affected model-fitted parameters for Fe(III) reduction kinetics. Using a suite of plasmid-based inducible circuits maintained by appropriate S. oneidensis knockout strains, we pinpointed construct/strain pairings that expressed cymA, mtrA, and mtrC with maximal dynamic range of Fe(III) reduction rate. These optimized EET gene constructs were employed to create Buffer and NOT gate architectures that predictably turn on and turn off EET flux, respectively, in response to isopropyl β-D-1-thiogalactopyranoside (IPTG). Furthermore, we found that response functions generated by these logic gates (i.e., EET activity vs inducer concentration) were comparable to those generated by conventional synthetic biology circuits, where fluorescent reporters are the output. Our results provide insight on programming EET activity with transcriptional logic gates and suggest that previously developed transcriptional circuitry can be adapted to predictably control EET flux.

Selective Gate Driving in Intelligent Power Modules

Due to practical limitations in the manufacturing of power semiconductor dies, high power modules are composed of several dies in parallel in order to meet the desired load current requirements. With careful attention to the design, modern insulated gate bipolar transistor (IGBT)-based power modules feature relatively balanced current distribution amongst the parallel dies. However, owing to the increased switching speeds of wide bandgap devices, i.e., silicon carbide (SiC), it is challenging to design the package to achieve both low-loss and balanced operation. In this article, a technique is proposed where the individual dies in a multidie power module can be selectively driven by a closely integrated gate buffer. Amongst the benefits achieved by selectively driving the die gates, a profiling of the power loss within the intelligent power module is enabled. Furthermore, a practical technique to estimate the individual die temperatures is presented, and using the same method, the on-state voltage of the power module during load current conduction can be estimated. Finally, it is experimentally demonstrated that the combination of individual junction temperature estimation and the selective gate driving can be used to increase the power density of the power module by better utilizing the component dies.

A BGR-Recursive Low-Dropout Regulator Achieving High PSR in the Low- to Mid-Frequency Range

This article proposes a bandgap reference (BGR) recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the BGR circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5- μ m 5-V CMOS devices. The PSR was measured to be –102 to –80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with C OUT ≥ 1 μ F. The proposed LDO consumes only 50 μ A at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response.

Magnetic vortex transistor based tri-state buffer Switch

Magnetic analogue of electronic gates are advantageous in many ways. There is no electron leakage, higher switching speed and more energy saving in a magnetic logic device compared to a semiconductor one. Recently, we proposed a magnetic vortex transistor and fan-out devices based on carefully coupled magnetic vortices in isolated nanomagnetic disks. Here, we demonstrate a new type of magnetic logic gate based upon asymmetric vortex transistor by using micromagnetic simulation. Depending upon two main features (topology) of magnetic vortex, circulation and polarity, the network can behave like a tri-state buffer. Considering the asymmetric magnetic vortex transistor as a unit, the logic gate has been formed where two such transistors are placed parallel and another one is placed at the output. Magnetic energy given in the input transistors is transferred to the output transistor with giant amplification, due to the movement of antivortex solitons through the magnetic stray field. The loss and gain of energy at the output transistor can be controlled only by manipulating the polarities of the middle vortices in input transistors. Due to the asymmetric energy transfer of the antivortex solitons, we have shown successful fan-in operation in this topologically symmetric system. A tri-state buffer gate with fan-in of two transistors can be formed. This gate can be used as a ‘Switch’ to the logic circuit and it has technological importance for energy transfer to large scale vortex networks.

Dynamic On-Resistance in GaN Power Devices: Mechanisms, Characterizations, and Modeling

Gallium nitride (GaN) power devices enable power electronic systems with enhanced power density and efficiency. Dynamic on-resistance ( $R_{\mathrm{\scriptscriptstyle ON}}$ ) degradation (or current collapse), originating from buffer trapping, surface trapping and gate instability, has been regarded as a primary challenge for the lateral GaN-on-Si power devices. In this paper, we present an overview and discussion of the mechanisms, characterizations, modeling, and solutions for the degradation of dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ in GaN power devices. The complex dynamics of acceptor/donor buffer traps and their impacts on dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ have been analyzed and revealed by TCAD simulations and high-voltage back-gating measurements. The gate instability-induced dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ increase in different GaN device technologies and the role of gate overdrive are also discussed. Wafer-level and board-level characterization techniques enabling accurate dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ evaluation are reviewed. The dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ performance of the state-of-the-art commercial GaN devices is presented, and a behavioral model with the dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ degradation taken into consideration has been implemented for circuit analysis. The latest progress in GaN device technologies for enhanced dynamic performance is also reviewed and discussed.