Dynamic On-Resistance in GaN Power Devices: Mechanisms, Characterizations, and Modeling

Abstract

Gallium nitride (GaN) power devices enable power electronic systems with enhanced power density and efficiency. Dynamic on-resistance ( $R_{\mathrm{\scriptscriptstyle ON}}$ ) degradation (or current collapse), originating from buffer trapping, surface trapping and gate instability, has been regarded as a primary challenge for the lateral GaN-on-Si power devices. In this paper, we present an overview and discussion of the mechanisms, characterizations, modeling, and solutions for the degradation of dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ in GaN power devices. The complex dynamics of acceptor/donor buffer traps and their impacts on dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ have been analyzed and revealed by TCAD simulations and high-voltage back-gating measurements. The gate instability-induced dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ increase in different GaN device technologies and the role of gate overdrive are also discussed. Wafer-level and board-level characterization techniques enabling accurate dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ evaluation are reviewed. The dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ performance of the state-of-the-art commercial GaN devices is presented, and a behavioral model with the dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ degradation taken into consideration has been implemented for circuit analysis. The latest progress in GaN device technologies for enhanced dynamic performance is also reviewed and discussed.