Buffer Design Research Articles

Holistic Sustainability Assessment of Riparian Buffer Designs: Evaluation of Alternative Buffer Policy Scenarios Integrating Stream Water Quality and Costs.

Riparian buffer zones (RBZs) have been shown to be effective best management practices (BMPs) in controlling non-point source pollutants in waterbodies. However, the holistic sustainability assessment of individual RBZ designs is lacking. We present a methodology for evaluating the holistic sustainability of RBZ policy scenarios by integrating environmental and economic indicators simulated in three watersheds in the southeastern USA. We developed three unique sets of 40, 32, and 48 RBZ policy scenarios as decision management objectives (DMOs), respectively, in Back Creek, Sycamore Creek, and Greens Mill Run watersheds (Virginia and North Carolina) by combining the RBZ-widths with vegetation types (grass, urban, naturalized, wildlife, three-zone forest, and two-zone forest). We adapted the RBZ-hydrologic and water quality system assessment data of instream water quality parameters (dissolved oxygen, total phosphorus, total nitrogen, total suspended solids-sediment and biochemical oxygen demand) as environmental indicators, recently published by U.S. EPA. We calculated 20-year net present value costs as economic indicators using the RBZ's establishment, maintenance, and opportunity costs data published by the Natural Resources Conservation Service. The mean normalized net present value costs varied by DMOs ranging from 4% (grass RBZ-1.9 m) to 500% (wildlife RBZ-91.4 m) across all watersheds, due primarily to the width and the opportunity costs. The mean normalized environmental indicators varied by watersheds, with the largest change in total nitrogen due to urban RBZs in Back Creek (60-95%), Sycamore Creek (37-91%), and Greens Mill (52-93%). The holistic sustainability assessments revealed the least to most sustainable DMOs for each watershed, from least sustainable wildlife RBZ (score of 0.54), three-zone forest RBZ (0.32), and three-zone forest RBZ (0.62), respectively, for Back Creek, Sycamore Creek, and Greens Mill, to most sustainable urban RBZ (1.00) for all watersheds.

Methodology for Structured Data-Path Implementation in VLSI Physical Design: A Case Study

State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence’s Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow.

Reliable Aluminum Wire-Bonded SiC/Si Diodes With Laminated Al/Cu Stress Buffers

Operation temperature of typical wire-bonded power modules, especially for harder silicon carbide (SiC) power chips, keeps increasing. The thermo-mechanical reliability of aluminum (Al) wire-bonds which suffer from the mismatch of coefficient of thermal expansion (CTE) between chip and bonding wires reduces significantly. In this letter, a novel laminated Al/copper (Cu) soft stress buffer was proposed between SiC chip and bonding wires, capable of reducing thermo-mechanical stress of the wires and using soft Al wires with low ultrasonic bonding energy instead sophisticated Cu wires. Lifetime of Al wire bonding on the proposed 10- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m Al/40- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m Cu buffer was 5.14 times longer than that on a SiC chip directly under power cycling with constant Δ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</sub> = 110 °C. In the end, a lifetime prediction model was established to guide the laminated buffer design for enhancing the reliability of Al wire-bonded Si diodes.

The DC Performance and RF Characteristics of GaN-Based HEMTs Improvement Using Graded AlGaN Back Barrier and Fe/C Co-Doped Buffer

In this article, the impact of the graded AlGaN back barrier and Fe\C co-doping buffer structure on the AlGaN <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$/$ </tex-math></inline-formula> GaN high electron mobility transistors (HEMTs) is proposed and systematically investigated. Due to effective suppression of Fe tail in unintentionally doped GaN (uid-GaN) layer by the insertion of the thick graded AlGaN back barrier layer, a large maximum drain current density and a transconductance peak are achieved. Meanwhile, the breakdown voltage is significantly improved by the use of Fe\C co-doping GaN buffer design. More importantly, it is revealed that the graded-AlGaN design can reduce the range and intensity of the electrical potential distribution in uid-GaN layer and then effectively suppress the acceptor-induced trapping\detrapping effect under high drain voltage. The RF small-signal performance of Fe-doped GaN (GaN:Fe)\C co-doping buffer HEMT exhibits significant improvement. In addition, load-pull measurement at 8 GHz revealed that a saturation power increases from 38.04 to 41.07 dB, a power gain increases from 9.06 to 10.58 dB, and an associate power-added-efficiency (PAE) increased from 40.27% to 50.18%. Our proposed GaN-based epitaxial structure can not only suppress the gate lag by reduce AlGaN surface electric field, but it can also suppress the drain lag by reduce the amplitude and range of potential distribution. It indicates that our proposed device has great potential for future high-voltage RF power amplifier application.

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

고 해상도 버퍼 설계를 통한 전달 정렬의 측정치 시간 지연 보상 기법

In this paper, we propose a time delay compensation method for transfer alignment using a high-resolution buffer design. Time delay degrades the performance of transfer alignment, resulting in subsequent mission failure. The value of such a time delay may not be constant and varies indefinitely depending on the system configuration or operating environment, which reduces the time delay estimation performance using general Kalman filtering. Using a state buffer is one of the methods to solve this problem. This paper presents a new time delay estimation method using a time delay candidate buffer. The proposed scheme can finely set the interval of time delay candidates and does not require a separate memory. In addition, a method for designing an appropriate time delay candidate buffer interval according to the activation of a vehicle and the performance of the MINS is presented. Simulations verified that the proposed technique could reduce the memory requirement and improve the transfer alignment performance for finely changing the time delay.

Saturated buffer design flow and performance in Illinois.

There are few peer-reviewed studies documenting saturated buffer annual nitrate (NO3 ) removal or that have assessed the federal practice standard design criteria. Drainage flow, NO3 , and dissolved reactive phosphorus (DRP) were monitored at three saturated buffers in Illinois, USA, for a combined 10 site-years. Nitrate loss reduction averaged 48 ± 19% with removals of 3.5-25.2kg NO3 -N ha-1 annually. Median DRP concentrations at all sampling locations were at the analytical detection limit of 0.01mg L-1 . The current design paradigm (i.e., USDA practice standard) prescribes there should be no flow bypassing the saturated buffer at flow rates that are ≤5% of the peak drainage system flow rate. The drainage coefficient-based and Manning's equation-based peak flow estimates were higher and lower, respectively, than the observed annual peaks in all years. This illustrated inherent uncertainty introduced early in the design process, which can be further compounded by dynamic in-buffer hydrology. The percentage of the observed peak flow rate at which bypass initiated ranged across an order of magnitude between sites (4.4-8.1% of peak flow rate at one site and 42-49% of peak at another) despite the buffers providing relatively similar NO3 removal. Bypass at one site (SB2) was related to the concept of "antecedent buffer capacity filled," which was defined as the 5-d average water depth in the middle control structure chamber expressed as a relative percentage of the bypass stop log height. This design flow analysis serves as a call to further evaluate predictive relationships and design models for edge-of-field practices.

Bionic Design and Analysis of a Novel Quadruped Robot with a Multistage Buffer System

Large quadruped mammals, such as ruminants, have outstanding motion ability, including running and bounding. These advanced motion abilities are related to the buffer effect of their complicated musculoskeletal systems. However, the buffer effect of most bio-robots is not satisfactory owing to the simple design of their buffer systems. In this paper, a physiological analysis of the ruminant musculoskeletal system is presented to explain the intrinsic buffer mechanism of motion. Based on the physical buffer parts of the ruminant limbs, the corresponding bionic mappings were determined. These mappings were used to guide the mechanism design of the robot multistage buffer system. The multistage buffer system includes two main buffer mechanisms: the first stage and the second stage. The buffer mechanism analysis of the first stage and multiple stages is discussed in theory to compare the effects between the normal single buffer system and the novel multistage buffer system. Then, the detailed mechanical structure of the limbs was designed based on the limb mechanism design. To further verify the superior efficacy of the multistage buffer system, the corresponding walking simulation experiments were conducted after the virtual prototype of a quadruped robot with a novel limb was built completely. Both theoretical analysis and simulation experiments prove that the bionic robot design with the novel multistage buffer system achieves better motion performance than the traditional robot buffer design and can be regarded as the design template of the robot limb.

How safe do you feel? – A large-scale survey concerning the subjective safety associated with different kinds of cycling lanes

There is ample evidence that adequate cycling infrastructure increases cyclists’ safety. There is less research to what extent the specific design of cycling lanes affects subjective safety. We address this question by analysing data from a large-scale online survey, where participants rated images illustrating a wide range of cycling infrastructure designs for the anticipated level of subjective safety when imagining to cycle at the displayed location. Cycling tracks are perceived as safer than cycling lanes, which in turn are preferred over cycling on the street. Physical separations from the car lane, a greater lane width, and a coloured surface contribute most to a high subjective safety of cycling lanes. Additional buffers on the left- and right side of cycling lanes can have varying effects. On narrower cycling lanes, people experience extensive buffer designs as rather constraining and as impairing their safety. Combining several safety features (i.e. a sufficient demarcation of the left buffer and a coloured surface) is not necessarily beneficial for subjective safety. Our findings are mostly in line with findings on the factors benefitting or impairing objective safety. However, the relation of subjective and objective safety requires further attention.

The Design of High-performance and Configurable Load Storage Unit

A high-performance configurable load storage unit (LSU) design is completed under the open source RISC-V framework. By compressing the pipeline depth, the module function structure is optimized under the premise of the control unit overhead, and the instruction processing speed is improved. In the method of instruction processing, a partial out-of-order processing strategy is adopted to control the increase of module complexity, reduce instruction blocking, and increase the density of instructions flowing into the LSU and the write back speed; redirection technology is adopted, and 3 channels are added when writing back data, which improve the speed of data write back, reduce instruction blocking, and ensure the correctness of the data; in order to support the partial out-of-order processing of the load and store instructions and the data redirection function, a double buffer design is adopted, the issue port and write-back port have been expanded to improve the transmission speed and write-back speed of the command. At the same time, the unit adopts a configurable way to expand the function, and separates the additional functions separately. It has good configurability and provides a good design for the next step of function expansion. Experimental results show that, after optimized design, LSU has increased the speed of existing processors by 63.5%, and has huge potential performance in processing high-density and read-related instructions, while the unit overhead has been reduced, the overall performance has been significantly improved.

Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse

In this article, we propose a hardware accelerator design using ferroelectric transistor (FeFET)-based hybrid precision synapse (HPS) for deep neural network (DNN) on-chip training. The drain erase scheme for FeFET programming is incorporated for both FeFET HPS design and FeFET buffer design. By using drain erase, high-density FeFET buffers can be integrated onchip to store the intermediate input-output activations and gradients, which reduces the energy consuming off-chip DRAM access. Architectural evaluation results show that the energy efficiency could be improved by 1.2× ∼ 2.1×, 3.9× ∼ 6.0× compared to the other HPS-based designs and emerging non-volatile memory baselines, respectively. The chip area is reduced by 19% ∼ 36% compared with designs using SRAM on-chip buffer even though the capacity of FeFET buffer is increased. Besides, by utilizing drain erase scheme for FeFET programming, the chip area is reduced by 11% ∼ 28.5% compared with the designs using body erase scheme.

Coupling novel Li7TaO6 surface buffering with bulk Ta-doping to achieve long-life sulfide-based all-solid-state lithium batteries

A coupling design of novel Li7TaO6 surface buffer coating with bulk Ta-doping for the NCM811 cathode with controllable surface thickness is successfully synthesized by a simple and scalable method, demonstrating excellent long-life performance in sulfide-based ASSLBs.

Optimal on-board energy buffer design for fuel-cell hybrid intercity vehicles

A long-distance or intercity bus has been the primary transport mode for people travelling across a country. Technological shift to the next-generation of electric vehicles marks a significant departure for traditional automakers and hence leads to develop zero-emission buses and utilising fuel cells (FC) is one of the potential alternatives. This paper proposes the optimal calculation of the energy storage in an FC hybrid intercity bus using either batteries or supercapacitors (SCs) as the main energy buffer. The long-distance driving cycle used is modified from the Highway Fuel Economy Driving Schedule and the mixed-integer PSO method is adopted. The design objective is to minimise the cost of the energy storage and FC, and hydrogen consumption of the total route. The results show and compare the optimal energy storage and FC sizing between the FC-battery and FC-SC buses. The FC-battery bus is cost-effective, and the battery capacity is also sufficient to supply all auxiliary loads during FC start-up. However, frequent charge and discharge cycles could shorten the battery's lifetime. From a hydrogen consumption viewpoint, the FC-SC bus is slightly more efficient because the FC always operates at a higher efficiency region, and it takes a shorter time to recharge the SC.

Negative capacitance FETs for energy efficient and hardware secure logic designs

Negative capacitance field effect transistors (NCFETs) have attracted good attention for energy efficient circuit designs. However, there are no clear design insights with NCFET based circuit designs for energy efficient and hardware secure applications. However, the lack of clear design insights make energy efficient and hardware secure NCFET circuit design more challenging. This paper presents important design insights and scope of NCFETs for energy efficient and hardware secure logic design at scaled supply voltages. Initially, NCFET device characteristics have been analyzed by varying the ferroelectric layer thickness (tfe) to identify optimum device performance window. At 40 nm technology node, NCFET device demonstrates enhanced characteristics for logic design with tfe in the range of 3 nm–5 nm due to steep subthreshold swing characteristics. NCFET with tfe of 5 nm exhibits 1.22 × higher ON current, 66 × lower leakage current and a SS of 50mV/dec compared to baseline MOSFET (tfe = 0 nm). Further, NCFET based static complementary inverter design exhibits better performance and higher energy efficiency compared to baseline MOSFET. NCFET inverter with tfe of 3 nm achieves optimum performance in terms of voltage transfer characteristics, differential gain, and noise margins. In addition, NCFET with tfe of 3 nm shows minimum energy consumption with the different supply voltages in the range of 0.6–0.8 V. Moreover, NCFET based buffer, logic gates and half-adder designs with tfe of 3 nm achieve approximately 3 × lower energy consumption compared to baseline designs. Apart from this, the NCFET designs exhibit 2 × higher ON current variations, 12 × higher inverter delay variations, and 3.1 × higher ring oscillator frequency variations compared to baseline designs against 5% process parameter variations at a supply voltage of 0.5 V. With the higher variations resulted from ferroelectric layer, NCFET demonstrate the potential and suitability towards the design of hardware security primitives like physically unclonable function (PUF) and true random number generator (TRNG).

Design and Flow Field Analysis of a New Mandrel Type Hydraulic Buffer

Design and Flow Field Analysis of a New Mandrel Type Hydraulic Buffer

Sensitivity of Riparian Buffer Designs to Climate Change-Nutrient and Sediment Loading to Streams: A Case Study in the Albemarle-Pamlico River Basins (USA) Using HAWQS.

Riparian buffer zones (RBZs) provide multiple benefits to watershed ecosystems. We aimed to conduct an extensive sensitivity analysis of the RBZ designs to climate change nutrient and sediment loadings to streams. We designed 135 simulation scenarios starting with the six baselines RBZs (grass, urban, two-zone forest, three-zone forest, wildlife, and naturalized) in three 12-digit Hydrologic Unit Code watersheds within the Albemarle-Pamlico river basin (USA). Using the hydrologic and water quality system (HAWQS), we assessed the sensitivity of the designs to five water quality indicator (WQI) parameters: dissolved oxygen (DO), total phosphorous (TP), total nitrogen (TN), sediment (SD), and biochemical oxygen demand (BD). To understand the climate mitigation potential of RBZs, we identified a subset of future climate change projection models of air temperature and precipitation using EPA's Locating and Selecting Scenarios Online tool. Analyses revealed optimal RBZ designs for the three watersheds. In terms of watershed ecosystem services sustainability, the optimal Urban RBZ in contemporary climate (1983-2018) reduced SD from 61-96%, TN from 34-55%, TP from 9-48%, and BD from 53-99%, and raised DO from 4-10% with respect to No-RBZ in the three watersheds. The late century's (2070-2099) extreme mean annual climate changes significantly increased the projected SD and BD; however, the addition of urban RBZs was projected to offset the climate change reducing SD from 28-94% and BD from 69-93% in the watersheds. All other types of RBZs are also projected to fully mitigate the climate change impacts on WQI parameters except three-zone RBZ.

Growth design for high quality AlxGa(1−x)N layer with high AlN-fraction on Si (1 1 1) substrate by MOCVD

The constraints on increasing the AlN content in active AlGaN device layers on Si substrates for AlGaN-channel HEMTs and UV applications are explored. The essential qualifications an AlGaN semiconductor material must satisfy to be used as functional device are crack free films, a surface roughness of <1 nm, dislocation densities approaching that of GaN (∼109 cm2) and a reasonable thickness of around 1 μm; each one of the material specifications demand a growth condition that is mostly unfavourable to achieve the other one. To meet these diversified requirements thorough optimisation of growth conditions is carried out. As a result, compositions containing up to 30% AlN-fraction have been achieved. This has been accomplished by understanding the role of growth temperature and buffer design on stress, defect and surface evolution in the AlGaN epilayers. Our studies show that higher AlN-fraction containing epilayers are achievable if stress relaxation during its growth is minimised while simultaneously keeping the growth front smooth under the given growth condition. Such a growth condition can be successfully exploited if the dislocation density at the beginning of epilayer growth is lowered. A smooth heterointerface between Al0.13Ga0.87N and Al0.37Ga0.63N has been realized and formation of 2DEG at this this interface has been confirmed through C-V measurements.

Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory

Internet routers/switches are vulnerable to system failures which require a power reset. Tremendous efforts are made to guarantee the high availability of the systems. A recent work shows that a phase change memory (PCM)-based routing lookup table can achieve high availability in the destination lookup of routers/switches. However, a packet buffer in routers/switches cannot benefit from the lookup table approach because it requires a much larger and higher-bandwidth memory system and its memory traffic is equally divided into reads and writes, while routing table accesses are mostly read-dominant. PCM can provide high availability even when the system undergoes a power reset but exhibits unacceptable write bandwidth. In this work, we propose a magnetic RAM (MRAM)/PCM-based hybrid memory packet buffer and a packet mapping method. A small MRAM combined with a large PCM can outperform the dynamic random access memory (DRAM)-based packet buffer by 28.5% or 22.4% on average for internet-mix packet traffic when optimizing only bandwidth or both bandwidth and lifetime. The proposed adaptive packet mapping method maps small packets less than a predetermined packet size threshold to MRAM for maximizing PCM bandwidth as small packets degrade row buffer locality in PCM. In addition, the mapping method dynamically changes the packet size threshold to capture the working set of packet buffering, which significantly improves PCM lifetime.

Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

PurposeThe small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput.Design/methodology/approachTo address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA.FindingsIn the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.Originality/valueIn the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

Design and implementation of a structural subsystem ofChang&amp;rsquo;e-5 probe

<p indent=0mm>The Chang’e-5 probe has achieved the first unmanned lunar surface sampling and return mission in China. The probe faced several technical challenges, including complex configuration, high lightweight and precision requirements, and strict environmental and load conditions. The design scheme of the whole structure and substructure of the probe is briefly introduced in this paper. Particularly, for key technical problems, such as the lunar surface sampling, lunar orbital rendezvous and docking, and returning lunar samples to the earth at high speed <sc>(11 km/s,</sc> close to the second cosmic velocity), this paper expounds on the research contents of the lightweight of the lander and ascender, high-precision composites structure design method, structure scheme of the takeoff platform with the integrated heat-resistant and load-bearing technology, design of the returner bond buffer to adapt to the impact of oblique landing, and labyrinthine thermal-seal design of the hatch door. The results of the mission show that the design of the structural subsystem of the Chang’e-5 probe is a complete success.