The Design of High-performance and Configurable Load Storage Unit

Abstract

A high-performance configurable load storage unit (LSU) design is completed under the open source RISC-V framework. By compressing the pipeline depth, the module function structure is optimized under the premise of the control unit overhead, and the instruction processing speed is improved. In the method of instruction processing, a partial out-of-order processing strategy is adopted to control the increase of module complexity, reduce instruction blocking, and increase the density of instructions flowing into the LSU and the write back speed; redirection technology is adopted, and 3 channels are added when writing back data, which improve the speed of data write back, reduce instruction blocking, and ensure the correctness of the data; in order to support the partial out-of-order processing of the load and store instructions and the data redirection function, a double buffer design is adopted, the issue port and write-back port have been expanded to improve the transmission speed and write-back speed of the command. At the same time, the unit adopts a configurable way to expand the function, and separates the additional functions separately. It has good configurability and provides a good design for the next step of function expansion. Experimental results show that, after optimized design, LSU has increased the speed of existing processors by 63.5%, and has huge potential performance in processing high-density and read-related instructions, while the unit overhead has been reduced, the overall performance has been significantly improved.