Abstract
The Arm architecture is a load–store architecture, which means that data processing instructions don't directly operate on data in memory. This chapter looks at different addressing modes and offset forms supported by these instructions. It starts with the basic load and store instructions. The load register instruction loads a 32-bit value from a memory address into a register. The chapter discusses several different types and modes of accessing memory. It provides the list of addressing modes supported on the A32 and A64 instruction sets. Load and store instructions using the offset addressing mode apply an offset to the base register value to form the memory address used for memory access. Pre-indexed addressing can be used in combination with the many different offset forms. The post-indexed addressing mode decouples the offset computation logic and the memory-access part of the instruction completely.
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