Breakdown Voltage Degradation Research Articles

Low-loss carrier stored trench-gate bipolar transistor with split-gate optimization

In the conventional carrier stored trench-gate bipolar transistor (CSTBT) device, a lower conduction voltage drop (Von) can be achieved with higher carrier stored (CS) layer dosage. However, the trench bottom is weakened leading to easier breakdown under high electrical field. In this work, the trench-gate structure of the conventional CSTBT is optimized and split into three components. The bottom and top left components of the split trench structure are equipotential with the emitter, which effectively eliminated the impact of collector on the trench gate with reduced gate charge (Qgc). In addition, another n-type CS layer is formed adjacent to the emitter to further enhance the hole carrier storage effect near emitter. This improves the trade-off between Von and turn-off time (Toff) without breakdown voltage (BV) degradation. The simulation results show that in comparison with the conventional CSTBT, the proposed device exhibits 64.6% reduction in Qgc under the same Von, while the turn-off time (Toff) and the saturation current are reduced by 14.9% and 43.4%, respectively. The short-circuit capability is also studied with 2.83 times improvement. Our proposed device shown here provides a feasible and attractive approach for advanced high-performance power electronics applications.

Single-event burnout resilient design of 4H-SiC MOSFETs through staircase-like buffer layer

With the rapid development of SiC materials, high-power devices such as SiC MOSFETs have been widely used in aerospace, new energy, nuclear applications, and other fields. This places higher demands on their reliability, especially about radiation effects. This paper proposes a 4H-SiC staircase-like buffer layer MOSFET (SBL-MOSFET) with a hardened structure against single-event burnout (SEB). A comparison is made with conventional VD-MOSFET, gauss buffer layer MOSFET (GBL-MOSFET), and double buffer layer MOSFET (DBL-MOSFET) through TCAD simulations. The performance of the SBL-MOSFET against single-event burnout is studied by investigating the electric field distribution, impact ionization rate, hole concentration, and lattice temperature. The simulation results demonstrate that the staircase-like buffer layer structure effectively improves the distribution of high electric field, reduces the impact ionization rate, and thus increases the SEB threshold voltage compared to other structures. The proposed SBL-MOSFET exhibits a 67.5 % improvement in single-event burnout threshold voltage compared to the conventional VD-MOSFET, with slight degradation of breakdown voltage and leakage current. Meanwhile, there is no significant change in other electrical parameters.

Breakdown-Voltage Degradation Under AC Stress of Thick SiO2 Capacitors for Galvanic Insulation

Breakdown-Voltage Degradation Under AC Stress of Thick SiO₂ Capacitors for Galvanic Insulation

Breakdown Characteristics of Ga2O3-on-SiC Metal-Oxide-Semiconductor Field-Effect Transistors

Ultra-wide bandgap semiconductor gallium oxide (Ga2O3) features a breakdown strength of 8 MV/cm and bulk mobility of up to 300 cm2V−1s−1, which is considered a promising candidate for next-generation power devices. However, its low thermal conductivity is reckoned to be a severe issue in the thermal management of high-power devices. The epitaxial integration of gallium oxide thin films on silicon carbide (SiC) substrates is a possible solution for tackling the cooling problems, yet premature breakdown at the Ga2O3/SiC interface would be introduced due to the relatively low breakdown strength of SiC (3.2 MV/cm). In this paper, the on-state properties as well as the breakdown characteristics of the Ga2O3-on-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) were investigated by using the technology computer-aided design (TCAD) approach. Compared with the full-Ga2O3 MOSFET, the lattice temperature of the Ga2O3-on-SiC MOSFET was decreased by nearly 100 °C thanks to the high thermal conductivity of SiC. However, a breakdown voltage degradation of >40% was found in an unoptimized Ga2O3-on-SiC MOSFET. Furthermore, by optimizing the device structure, the breakdown voltage degradation of the Ga2O3-on-SiC MOSFET is significantly relieved. As a result, this work demonstrates the existence of premature breakdown in the Ga2O3-on-SiC MOSFET and provides feasible approaches to further enhance the performance of hetero-integrated Ga2O3 power devices.

Ultra-high voltage silicon pixel sensor with less soft-breakdown for X-ray free electron laser

X-ray free electron laser (XFEL) requires operation of an advanced silicon pixel sensor (SPS) under ultra-high voltage for detection of fast electron–hole pairs. In this study, a high-voltage tolerant SPS is designed and fabricated by considering suppressing the soft-breakdown of the current collection ring (CCR) and increasing the breakdown voltage of the pixel array after dicing the sensor. It is found that a soft-breakdown behavior of CCR in one diced SPS occurred before a hard breakdown happening in the pixel and it may cause the degradation of maximum hard breakdown voltage in pixel region, which, in particular, turns worse as the increasing of the number of guard rings. An optimized method with the expansion of the non-sensitive area is used to effectively prevent the occurrence of soft-breakdown and increase the operation voltage of the SPS. Ultimately, a high performance SPS with a maximum breakdown voltage exceeding 1000 V and reversed leakage of ∼1.5 pA per pixel at bias 500 V is obtained. Together with the optimized multi-guard ring structure, a record ultra-high avalanche breakdown voltage of over 2100 V is obtained, which provides a promising approach to develop ultra-fast detector in an XFEL.

New Insight Into Total-Ionizing-Dose Effect-Induced Breakdown Voltage Degradation for SOI LDMOS: Irradiation Charge Field Modulation

In this article, the concept of irradiation charge field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> ) is proposed to provide a new insight into total-ionizing-dose (TID) effect-induced breakdown voltage (BV) degradation for high-voltage silicon-on-insulator (SOI) lateral double-diffused metal–oxide-silicon (LDMOS). A unified explanation on TID-induced BV degradation is given that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> exerts modulation on net electric field, changing the relationship between lateral BV (BVL) and vertical BV (BVV). <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> would weaken electric field at silicon side of silicon/buried oxide interface and enhance that at oxide side, resulting in BVV increasing monotonously. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {rc}}$ </tex-math></inline-formula> would also weaken surface electric field at drain side and enhance that at source side, resulting in BVL changing with two potential trends: monotonic descent and nonmonotonic descent, corresponding to different initial surface breakdown points. Eventual BV degradation is determined by the combined result of BVV and BVL changing. Based on the new insight, a radiation hardening design strategy is proposed. Nonuniform initial surface electric field distribution with single drain peak is pursued, breaking the conventional optimization principle. Nonmonotonic descent of BV is achieved to enhance TID tolerance and verified by the developed 80-V SOI LDMOS with the proposed radiation hardening strategy.

Effect of Double Insulators on the Performance Improvement of 3 MeV Proton-Irradiated AlGaN/GaN MIS-HEMTs

To improve the performance of AlGaN/GaN high electron mobility transistors (HEMTs) after exposure to high energy proton irradiation, a MIS-HEMT with Al2O3/SiNx (SiNx next to semiconductor) double insulators is proposed and fabricated. Besides, the common Schottky gate HEMT and MISHEMTs with single SiNx layer and single Al2O3 layer are also fabricated as a control for comparison. After exposed to 3 MeV proton irradiation with a fluence of 1 × 1014cm−2, the MIS-HEMT with Al2O3/SiNx double insulators shows the smallest drain saturation current and breakdown voltage degradation, the smallest voltage drift and interface charge change through IV and CV tests. The smallest degradation of the carrier density and mobility contributes to its better saturation current degradation performance. Besides, experimental results of voltage drift are in accordance with simulation results. What’s more, the MIS-HEMT with Al2O3/SiNx double insulators exhibits the lowest drain current degradation and the quickest response during hard switching tests. A relatively large displacement threshold energy of Al2O3 and better passivation effect of SiNx contribute to the reliability improvement of AlGaN/GaN HEMTs after the proton-irradiation.

Investigation of breakdown voltage degradation in low-voltage narrow gate trench MOSFET by edge termination optimization

In this paper, we investigate breakdown voltage degradation in a 25 V low-voltage narrow gate (NG) shield-gate trench MOSFET (NG-SGTMOS). Experiments and simulations based on Technology Computer-Aided Design (TCAD) indicate that electric field crowding and parasitic bipolar junction transistor (BJT) punch-through are responsible for the degradation of the device breakdown characteristic. To address these issues, two critical parameters, t 1 and t 2, are optimized in the layout of the transition and termination regions of the experimental NG-SGTMOS. It is demonstrated that electric field crowding induced by excessive and non-full depletion in edge termination is successfully eliminated at t 1 = 0.6 μm. Moreover, when improving t 2 beyond 0.2 μm, the soft breakdown characteristic owing to parasitic npn-BJT punch-through can be suppressed. As a result, the breakdown voltage stability of the proposed low-voltage NG-SGTMOS is improved.

Performance evaluation of superjunction UMOS with dual polysilicon gate

A modified Superjunction (SJ) UMOS employing dual polysilicon material that is P+ polysilicon and N+ polysilicon on lower and upper portion of gate respectively is proposed in this paper. The proposed structure exploits the advantage of workfunction engineering at the gate electrode. The workfunction variation along the channel leads to increment in the transconductance and reduction in on resistance. The electrical characteristics of conventional SJ UMOS and proposed SJ UMOS have been simulated using ATLAS. The simulation results reveal 14.1% reduction in the resistance without any degradation in breakdown voltage. Further, transconductance and Baliga's Figure of Merit has also been calculated indicating 25% and 16.4% increment respectively for proposed structure signifying enhanced performance. The impact of temperature on the device behavior is also analyzed and it is suggested that the proposed device performs better than the conventional device even at higher temperature.

An insulated gate bipolar transistor with three-layer poly gate for improved figure of merit

In this study, an insulated gate bipolar transistor (IGBT) with three-layer poly gate is proposed and investigated by TCAD simulation. Here, gate is spilt in two different workfunction materials of N+ poly ( $$\phi _{g}$$ = 4.17 eV) and P+ poly ( $$\phi _{g}$$ = 5.25 eV). Lower workfunction poly layer is sandwiched between higher workfunction poly, connected via a single metal. The gate oxide thickness is varied in x-direction. This leads to improvement in transconductance and reduction in miller capacitance. Thin oxide near the emitter serves good control over the charge carriers in the channel. This deployment of dual material gate in proposed device results in 36% reduction in area-specific on-resistance without any degradation in breakdown voltage. In addition to this, proposed device exhibits improved transient characteristics with 18.5% and 60% reduction in turn-off time and delay, respectively, as compared to conventional device. Further, the turn-off energy loss is reduced by 23.5% and 29.09% reduction in on-state voltage drop is achieved. Furthermore, proposed device offers 23%, 58%, and 30% improvement in FOM1, Baliga figure of merit (BFOM), and FOM2, respectively.

A novel 4H-SiC MOSFET for low switching loss and high-reliability applications

A novel 1200 V 4H-SiC MOSFET, which features a current spreading layer, a split-gate and a central P+ implant in the junction field effect transistor region (CSI-MOSFET), is proposed. The CSI-MOSFET achieves a better trade-off among specific on-resistance, maximum electric field in gate oxide and switching loss. The CSI-MOSFET is comprehensively optimized with numerical simulation, and then two kinds of CSI-MOSFETs (FCSI-MOSFET and GCSI-MOSFET with a floating/grounded central P+ implant) are further investigated. Compared with the conventional double implanted MOSFET (VDMOSFET), both FCSI-MOSFET and GCSI-MOSFET demonstrate a smaller on-resistance, and a smaller gate charge. Moreover, a maximum electric field in the gate oxide of 0.92 MV cm−1 is realized in GCSI-MOSFET, without breakdown voltage degradation. To our best knowledge, it is the lowest electric field among those reported on 1200 V SiC MOSFETs. For dynamic characteristics, the FCSI-MOSFET has the largest switching loss and the largest on-state voltage drop, due to the negative charges stored in the floating P+ implant region. On the contrary, the GCSI-MOSFET achieves the same low switching loss as that of the split-gate MOSFET with an extreme short gate length (0.2 μm), because there is no charge in the grounded P+ implant region. Therefore, the GCSI-MOSFET is far superior for low switching loss and high-reliability applications.

TID-Induced Breakdown Voltage Degradation in Uniform and Linear Variable Doping SOI p-LDMOSFETs

The breakdown voltage (BVDS) of uniform doping (UD) and linear variable doping (LVD) silicon-on-insulator (SOI) p-channel laterally diffused metal oxide semiconductor field effect transistors (p-LDMOSFETs) is examined after exposure to the total ionizing dose (TID). The results show BVDS degradation with accumulated dose. TID degradation with the MOS device biased off is more severe than that with the MOS device biased on. Also, LVD BVDS is more significant than UD BVDS at a given TID. Technology computer-aided design (TCAD) simulation is used to gain an insight into the mechanism causing BVDS degradation.

Impact of Electrical Stress and Neutron Irradiation on Reliability of Silicon Carbide Power MOSFET

The combined effects of electrical stress and neutron irradiation of the last generation of commercial discrete silicon carbide power MOSFETs are studied. The single-event burnout (SEB) sensitivity during neutron irradiation is analyzed for unstressed and electrically stressed devices. For surviving devices, a comprehensive study of the breakdown voltage degradation is performed by coupling the electrical stress and irradiation effects. In addition, mutual influences between electrical stress and radiative constraints are investigated through TCAD modeling.

Total Ionizing Dose Effects in 30-V Split-Gate Trench VDMOS

In this article, the total ionizing dose (TID) effect is investigated in the 30-V split-gate trench (SGT) Vertical double diffused MOSFET (VDMOS). The complex trench structure, including gate oxide, split-gate oxide, and isolation oxide, is carefully studied to reveal the degradation mechanisms. Due to the multioxidation and annealing processes, the trench structure suffers serious oxide defeats. The analytical result shows a larger trapping efficiency ( ${f}_{{\text {ot}}}$ ) compared to the planar gate technology, leading to significant ${V}_{{\text {th}}}$ shifts and subthreshold leakage. Meanwhile, irradiation-induced trapped charges in the split-gate oxide have a great influence on the electric field profile in bulk, which gives rise to breakdown voltage (BV) degradation. The experimental result shows that BV presents a gradient descent and drops to as low as 14 V at 100 krad(Si). Through TCAD simulation and analytical calculation, these TID responses are evaluated, and three approaches have been proposed for the radiation hardness of SGT VDMOS.

600-V shielded trench split-gate VDMOS improving the figure of merit

ABSTRACT A shielded trench split-gate vertical double-diffused metal-oxide-semiconductor field-effect transistor (ST-SG-VDMOS) is proposed, and the analytical model for the main components of specific on-resistance (R on,sp) is derived. The polysilicon vertical field plate (VFP) with the thick oxide layer in every trench modulates the electric field distribution to ensure no degradation of breakdown voltage (BV). Moreover, due to the strong assistant depletion effect caused by VFPs, R on,sp is effectively reduced by increasing the doping concentration among trenches. Not only the gate is shielded from the drain bias by VFPs, but also the split-gate structure is adopted to reduce the specific gate-drain charge (Q gd,sp). When compared to the conventional VDMOS (C-VDMOS) in 600 V class, the simulation results by the technology computer aided design (TCAD) show that the R on,sp and Q gd,sp in ST-SG-VDMOS decrease from 128.8 to 85.77 mΩ·cm2 and from 88.3 to 14.1 nC/cm2, respectively. Finally, the product of R on,sp and Q gd,sp called as figure of merit is reduced by 89.4% in the ST-SG-VDMOS. The performance of ST-SG-VDMOS has been significantly improved when compared with C-VDMOS.

The impact of heavy ion irradiation on the performance of novel REDI LDMOS power devices

In this paper, the impact of heavy ion irradiation on the performance of novel REDI LDMOS (RESURF Dielectric Inserted Lateral Double-diffused MOS transistor) power devices is experimentally investigated for the first time. The performance degradation of REDI LDMOS caused by micro-dose effect and displacement damage (DD) is demonstrated, and the impact of ion fluence and device geometry is analysed. Different degradation behavior occur due to the intrinsic random incident of heavy ions. The threshold voltage (Vth) of the device is barely changed after irradiation. The off-state leakage current (Ioff) of the device may increase or decrease after irradiation, which can change by up to 2 orders of magnitude. The breakdown voltage (BV) of REDI LDMOS may decrease by up to 50%. In addition, the on-resistance (Ron) and on-state current (Ion) of the device are changed by up to about 40%. Further, heavy ion fluence has significant effect on device characteristics after irradiation. For low-fluence (5 × 108 ions cm−2), the degradation of BV is the main problem caused by irradiation. And BV, Ron and Ion degradation should be paid attention for devices irradiated by high-fluence (5 × 109 ions cm−2) heavy ion. Besides, the distance between p+ region and the drift region boundary (LD) has negligible effect on the performance degradation of the irradiated device. However, the maximum value and variation of BV degradation of devices irradiated by high-fluence heavy ion increase with the increase of the length of the gate overlap the drift region (Lov). The results are of great significance for the research of the radiation-hardened technology of power devices.

AgCrO2 formation mechanism during silver inner electrode and Fe–Si–Cr alloy powder co-firing in metal multilayer chip power inductors

Multilayer Fe–Si–Cr alloy chip power inductors have the benefits of a smaller, thinner profile, lower DC resistance and higher rated current. During metal multilayer power inductor co-firing, Fe–Si–Cr alloy powders react with the inner electrode, silver, to form a large amount of hexagonal flaky AgCrO2. The p-type semiconductor, AgCrO2, will cause co-fired Fe–Si–Cr alloy multilayer chip power inductor insulation degradation, hence reducing the power conversion efficiency due to the increase in eddy current loss. The AgCrO2 forming mechanism is investigated in this study. It was observed that silver reacts with the Fe–Si–Cr thermal grown oxide layer, Cr2O3, and subsequently leads to the formation of Ag2CrO4 when the temperature is lower than 650 °C. The formed Ag2CrO4 with low melting temperature then volatilizes at higher temperatures through the pore channels to react with the volatilized Cr2O3 to form the AgCrO2. AgCrO2 will cause Fe–Si–Cr alloy multilayer chip inductor resistivity and breakdown voltage degradation.

Thermal Aging Characteristics of Newly Synthesized Triester Insulation Oil

High-stability triester insulation oil derived from the trimethylolpropane esters (TME) was synthesized by esterifying saturated fatty acids and trimethylolpropane (TMP). The TME oil shows higher AC breakdown voltage (Vb, 72.6 kV/2.5 mm) than that of FR3 (65 kV/2.5 mm). TME oil is readily biodegradable whose biodegradation is 82.2% after 28 days. Pressurized differential scanning calorimetry (PDSC) was applied to measure oxidation onset temperature (OOT) of TME oil for initial evaluating the oxidation stability. Due to the elimination of the carbon-carbon double bonds and β-H, the OOT of the TME oil without antioxidants is approximately 25°C higher than that of FR3. To evaluate the realistic performance of the TME oil, the effect of transformer materials on the aging behavior was investigated. The effect of transformer materials on the thermal aging of TME oil and mineral oil (MO) is less than that of FR3. Although the moisture content and acid value in TME oil induced by aging are higher than those in MO. These acids and moisture do not cause obvious degradation of breakdown voltage and dielectric loss factor, which may be attributed to the high moisture solubility in it.

Impact of rounded electrode corners on breakdown characteristics of AlGaN/GaN high-electron mobility transistors

We investigated the impact of rounded electrode corners on the breakdown characteristics of AlGaN/GaN high-electron mobility transistors. For standard reference devices, catastrophic breakdown occurred predominantly near the sharp electrode corners. By introducing a rounded-electrode architecture, premature breakdown at the corners was mitigated. Moreover, the rate of breakdown voltage (VBR) degradation with an increasing gate width (WG) was significantly lower for devices with rounded corners. When WG was increased from 100 µm to 10 mm, the VBR of the reference device dropped drastically, from 1,200 to 300 V, whereas that of the rounded-electrode device only decreased to a respectable value of 730 V.

Interface Si donor control to improve dynamic performance of AlGaN/GaN MIS-HEMTs

In this letter, we have studied the performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with different interface Si donor incorporation which is tuned during the deposition process of LPCVD-SiNx which is adopted as gate dielectric and passivation layer. Current collapse of the MIS-HEMTs without field plate is suppressed more effectively by increasing the SiH2Cl2/NH3 flow ratio and the normalized dynamic on-resistance (RON) is reduced two orders magnitude after off-state VDS stress of 600 V for 10 ms. Through interface characterization, we have found that the interface deep-level traps distribution with high Si donor incorporation by increasing the SiH2Cl2/NH3 flow ratio is lowered. It’s indicated that the Si donors are most likely to fill and screen the deep-level traps at the interface resulting in the suppression of slow trapping process and the virtual gate effect. Although the Si donor incorporation brings about the increase of gate leakage current (IGS), no clear degradation of breakdown voltage can be seen by choosing appropriate SiH2Cl2/NH3 flow ratio.