Bottom-gate Structure Research Articles

Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge0.95Sn0.05 Film Formed by Amorphous GeSn Deposition and Annealing

A systematic investigation on the formation of poly-GeSn film by depositing amorphous GeSn film and subsequent annealing was carried out in this letter to implement high-performance p-channel junctionless thin-film transistors. By using planar devices with the bottom gate structure as the platform, the optimal process condition for forming the poly-GeSn film including annealing temperature, time, and film thickness was determined by X-ray diffraction analysis and device characteristics. It is found that the amorphous GeSn film starts to crystallize at 450 °C and corresponds to better film quality by increasing the temperature to 500 °C. In addition, the film crystallinity is hardly affected as the annealing time exceeds 30 s. With the film thickness in the range between 60 and 12 nm, thinner thickness is beneficial for device operation since it can be turned off more efficiently. Based on the results, then various annealing ambient such as Ar, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O were employed to study its impact on the device performance. Ar-annealed devices exhibit the best performance in terms of the largest drive current capability which is primarily ascribed to the smallest grain boundary density from the largest grain size and the reduced bulk trap density from better defect passivation effect of the dangling bonds in the poly-GeSn film. Even with planar device structure, Ar-annealed devices also demonstrate high ION/IOFF ratio up to 1.7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> which is due to the good poly-GeSn quality. Moreover, the low-thermal-budget process of 500 °C/30 s paves a new avenue to empower high-performance monolithic 3-D ICs.

Degradation on the Current Saturation of Output Characteristics in Amorphous InGaZnO Thin-Film Transistors

Degradation on the current saturation of the output characteristics in amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors with the bottom-gate structure is investigated. As the drain-to-source voltage ( ${V}_{\textsf {DS}}$ ) increases at a fixed gate-to-source voltage ( ${V}_{\textsf {GS}}$ ), the current from drain to source ( ${I}_{\textsf {DS}}$ ) becomes nonsaturated and increases due to the mobility enhancement and ${I}_{\textsf {DS}}$ also decreases again due to the electron trapping into the gate insulator and/or an interface, which occurs mainly at the channel edge near a drain. Analysis is validated by using the pulsed ${I}_{\textsf {DS}}$ – ${V}_{\textsf {DS}}$ measurement. Nonsaturated current is attributed to the Joule heating-assisted mobility enhancement and the thermally activated electron trapping, which is the reason why the nonsaturation becomes more prominent as the IGZO active thin film becomes thinner. Furthermore, it is found that the rate of the increased ${I}_{\textsf {DS}}$ per increasing ${V}_{\textsf {DS}}$ gets higher as either the channel width ( ${W}$ ) increases or the channel length ( ${L}$ ) decreases; whereas, the rate of the decreased ${I}_{\textsf {DS}}$ per increasing ${V}_{\textsf {DS}}$ becomes higher as the device size, i.e., ${W}\times {L}$ , increases. The former is well correlated with Joule heating while the latter with the self-heating-assisted electron trapping due to a total heat accumulated in an active layer.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing the Low-Temperature Polycrystalline-Si (LTPS) as their active areas are very crucial for the system-on-glass (SOG). The liquid-crystal display (LCD) or organic light emitting diode display are fabricated in the display area and their controls are performed by the micro-computer that is formed in the peripheral area. The application of high-performance poly-Si TFTs to the high-definition LCD light valves for projectors was reported for the first time[1]. Therefore, the requirements for the recrystallized Si film are a high quality, a large grain formation and a position control of the nucleation. To satisfy those requirements, a super lateral growth (SLG)[2] using the excimer laser annealing (ELA), a phase-modulated ELA[3], a solid-phase crystallization followed by ELA[1], a low-temperature solid-phase excimer laser crystallization[4], a Pd:YAG laser crystallization[5], a soft X-ray crystallization (SXC)[6] have been studied. For the device structure, the double gate TFT[7] and the tunnel TFT[8] have been developed. In our group, the low-temperature crystallization methods and the novel TFT utilizing tunnel effect have been researched. Low-temperature crystallization: For the ELA method, the mechanism of multi-pulse ELA crystallization has been clarified and a large grained film with a high-quality[4] was provided. In addition, hydrogens in a-Si film greatly influenced the crystallinity and grain size of the poly-Si[9,10] and we discovered the advantage in ELA of hydrogen–modulation-doped a-Silicon Layer[11]. For the SXC, a low-temperature crystallization of a-Si, Ge and SixGe1-x film was researched and developed using the short undulator as a light source. The fundamental process of the SXC-method is a local excitation of core electrons to vacuum level by photons followed by the atom movement due to the Coulomb repulsion, which results in the lower temperature process. The SXC-method reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x film by 100 - 150 degree C as compared with the conv. thermal crystallization. Novel TFT: Although the high-performance TFT with the high carrier mobility and low leakage current utilizing the large single crystalline grains has been intensively researched, it does not successfully operates from the productive viewpoint[12]. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated in a bottom-gate structure. Using a 1.7-nm-thick SiNx film, it reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect as shown in Fig.1[13]. It is considered that the fixed charge in the SiNx film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion. We conclude that TDTFT will suitable as a candidate of the next generation TFT structure.

(Invited) High Density IGZO Film for Highly Reliable TFT By Inductively Coupled Plasma Sputtering Technology in Low Temperature Process

Transparent amorphous oxide semiconductors (TAOS) represented by IGZO have excellent characteristics such as high mobility, and a low off current compared with amorphous Si (a-Si) semiconductor. Furthermore, TAOS can be deposit by standard sputtering systems. Large area fabrication at a lower cost than low temperature polysilicon semiconductor (LTPS) is also possible. Therefore, there is a possibility to manufacture a display with high definition / low power consumption at low cost. However, many studies have shown the insufficient electrical reliability of IGZO TFTs. Although application to flexible displays is expected, in the conventional fabrication of IGZO TFTs, post annealing processes at a high temperature of 300°C is necessary. Therefore, low temperature formation of IGZO TFT is required. The inductively coupled plasma (ICP) sputtering system under development is characterized by its capacity to deposit high density films and high target usage efficiency. Figure 1 shows the schematic of the ICP sputtering system. In this system, the antenna is installed in the chamber, and a high-frequency generator is connected to the antenna. ICP is generated in the chamber by applying high-frequency to the antennas. In this device, since the magnetic field is not arranged on the target, ICP diffuses uniformly into the chamber. In order to perform sputtering, a negative bias voltage is applied to the target, ions are pulled from the ICP, and the target material is deposited on the substrate. The target material was uniformly consumed, and usage efficiency showed a very high value of 85%. In addition, since antennas and targets are connected to independent power supplies, independent control is possible. By increasing the high-frequency power applied to the antennas and controlling the plasma density, deposition is possible without lowering deposition rate even at low target voltage. We considered that independent control of RF power and target voltage is important because both may be related to film density. The density of the IGZO films deposited by changing the RF power and the target voltage was obtained using X-ray reflectivity. The results are shown in figures 2 (a) and (b). The relationship between RF power and film density could not be confirmed. When the target voltage was increased, the film density decreased. Therefore, performing deposition at a lower target voltage yielded a high-density IGZO film. Under all conditions, the IGZO films exhibited a film density of more than 6.0 g/cm3. In this study, the bottom-gate top-contact TFTs were fabricated by low-temperature process using high-density two-layer structure IGZO film deposited by ICP sputtering system, and the transfer characteristics and reliability were examined. Bottom-gate top-contact TFTs structure is shown in figure 3. The two-layer structure IGZO (In:Ga:Zn = 1:1:1) films were deposited by ICP sputtering system with different O2/Ar gas ratio condition at room temperature. The TFTs were subjected to post annealing at 150°C or 200°C or 250°C for 2 h under the O2/N2 mixed gas atmosphere. The passivation of the photosensitive polysilsesquioxane was coated using a straightforward solution process for samples annealed at 250°C, and baked at 250°C. The TFTs were subjected to a positive gate bias stress test (PBS) by applying a gate voltage (V gs) of 20 V, for a total stress time of 10000 s. Figure 4 show transfer characteristics of each post annealing temperature. When no annealing is performed, the TFT shows switching behavior but the threshold voltage (V th) became negative. When post annealing was carried out, V th became positive. Transfer characteristics at annealing temperature of 150°C to 250°C exhibited similar values. The electric field effect mobility of V ds = 0.5 V obtained from the transfer characteristic at post annealing temperature of 150°C was 7.9 to 8.8 cm2/Vs. The results of PBS are shown in figure 5. Threshold voltage shift (ΔV th) was used as an index of reliability. ΔV th of post annealing temperature of 150°C, 200°C and 250°C were 0.73 V, 0.75 V, 0.66 V, respectively. A sample with post annealing temperature at 250°C coated with polysilsesquioxane passivation has a ΔV th = 0.09 V. The reason why TFTs showing comparatively high-mobility can be fabricated even through a low-temperature process is considered to be the deposition of high-density films with low vacancy after deposition by the ICP sputtering system. In addition, it was found that the TFT with the annealing temperature of 150°C has the same reliability as the TFT with the annealing temperature of 250°C. We are set to demonstrate TFTs showing high-reliability at low-temperature process by using passivation that can be coated even at low temperatures. Figure 1

(Invited) Nanoscale Electrocrystallization: A Site-Selective Electrochemical π-Figuration of Nanocrystals for Electronic Devices

Efficient nanofabrication is still the problem awaiting solution in the nanotechnology field. Such nanofabrication should involve both economy and ecology-friendly process which produces high performance materials or devices. As seen in semiconductor industry, these fabrication technologies generally consume a large amount of energy under high-vacuum and/or high-temperature conditions. There is a strong need to switch to processes which are both eco-friendly and low-cost. Therefore pinpoint nanofabrication via eco-friendly process seems to be most promising. From the viewpoint, we have developed nanoscale electrocrystallization for nanodevice fabrication.1 This method allows everyone to grow nanocrystals, which consist of π-conjugated molecules, site-selectively within a gap between two electrodes fabricated on a substrate. In addition, this method also allows for the gap between the two electrodes to be bridged by the formed nanocrystals. · Magnetic field effect devices Magnetic field effect devices were designed by using dicyanoiron(III)phthalocyanine ([Fe(Pc)(CN)2]-) tetraphenylphosphonium (TPP+) salt as a starting material of nanoscale electrocrystallization. The electrolysis gave nanocrystals that exhibited a strong correlation between the localized spin and conduction electrons, TPP·[Fe(Pc)(CN)2]2 was obtained. A negative giant magnetoresistance was first observed as an organic nanocrystal.2 Moreover, an angular dependence of the negative giant magnetoresistance that originates from the highly oriented growth of the nanocrystals was also observed. · Electronic field effect devices Electronic field effect devices such as field-effect transistors (FETs) were designed by using materials for organic conductors. A bottom-gate type FET structure was simply obtained when a silicon substrate with oxide layer was used for an electrode substrate. The two electrochemical electrodes were reused as source and drain electrodes. FET characteristics showed current enhancement in some kinds of samples.3 The device fabrication was also demonstrated via an eco-friendly and non-vacuum process using a material printer.4 Further details of fabrication, materials, and physical properties will be reported.

Preparation and electrical properties of N-doped ZnSnO thin film transistors

The preparation and electrical properties of N-doped ZnSnO (ZTO: N) thin film transistor (TFT) with a staggered bottom-gate structure were studied in this paper. ZTO: N thin film, which served as the active layer of the prepared TFT, was deposited on SiO2/p-type Si substrates by radio frequency magnetron sputtering at room temperature. Secondary ion mass spectroscopy (SIMS) analysis results showed all the species (Zn, O, Sn and N) were uniformly distributed in the thin film. X-ray Diffraction (XRD) patterns and scanning electron micrograph (SEM) images indicated that the thin film transformed from amorphous to crystalline states due to annealing. X-ray photoelectron spectra (XPS) proved that the oxygen-related defects in the thin film decreased after annealing. The thin film before and after annealing both showed a good optical transmittance of over 80% in visible light region. The TFT prepared with the thin film exhibited n-channel enhancement mode behavior and showed good electrical properties with a saturation mobility of 41.8 cm2V−1s−1, a threshold voltage of 5.4 V, and an on/off current ratio of 6.5 × 107.

Effects of vacuum rapid thermal annealing on the electrical characteristics of amorphous indium gallium zinc oxide thin films

We investigated the effects of vacuum rapid thermal annealing (RTA) on the electrical characteristics of amorphous indium gallium zinc oxide (a-IGZO) thin films. The a-IGZO films deposited by radiofrequency sputtering were subjected to vacuum annealing under various temperature and pressure conditions with the RTA system. The carrier concentration was evaluated by Hall measurement; the electron concentration of the a-IGZO film increased and the resistivity decreased as the RTA temperature increased under vacuum conditions. In a-IGZO thin-film transistors (TFTs) with a bottom-gate top-contact structure, the threshold voltage decreased and the leakage current increased as the vacuum RTA temperature increased. As the annealing pressure decreased, the threshold voltage decreased, and the leakage current increased. X-ray photoelectron spectroscopy indicated changes in the lattice oxygen and oxygen vacancies of the a-IGZO films after vacuum RTA. At higher annealing temperatures, the lattice oxygen decreased and oxygen vacancies increased, which suggests that oxygen was diffused out in a reduced pressure atmosphere. The formation of oxygen vacancies increased the electron concentration, which consequently increased the conductivity of the a-IGZO films and reduced the threshold voltage of the TFTs. The results showed that the oxygen vacancies and electron concentrations of the a-IGZO thin films changed with the vacuum RTA conditions and that high-temperature RTA treatment at low pressure converted the IGZO thin film to a conductor.

Fabrication of Tin Oxide Thin Film Transistors by RF Magnetron Sputtering Using Sn/SnO Composite Target

P-type tin oxide thin film deposited by RF sputtering for transparent thin film transistor (TFT) applications is the subject of this study. P-type tin oxide thin film can be made by doping a cation with a lower valence into n-type SnO 2 as an acceptor impurity or by fabrication with tin monoxide (SnO). The later method was investigated in this study by RF magnetron sputtering process, which has a high deposition rate, uniform thickness control, simple stoichiometry control, and reproducibility. A Sn/SnO composite target was used in RF sputtering to utilize the benefits of both metallic and ceramic sputtering targets. A Sn/SnO composite target is expected to provide p-type tin oxide thin films that are easier to manufacture than metallic target or ceramic target. The metallic Sn element provides an excellent control of structural defects, while the ceramic SnO element provides stable stoichiometry. The p-type tin oxide thin film with a Sn/SnO composite target showed very good transparency of ~95%. and excellent electrical properties. The p-type tin oxide thin film of 15nm thickness had a carrier concentration of 8.03X10 15 cm -3 and a mobility of 15.2cm 2 /Vs. With these ultrathin tin oxide films, a p-channel TFT was fabricated with a staggered bottom-gate structure, and the effect of different channel thicknesses and different distances between the two electrodes were evaluated. The tin oxide TFT with a thick p-channel layer showed a significant increase in current measured than the tin oxide with a thin p-channel layer. The current measured tended to increase greatly as the distance between electrodes decreased. The IV output curves of the tin oxide TFTs exhibited characteristics of bipolar transistors potentially due to the partial creation of the oxygen-deficient SnO 2 like structure, but the mechanism of bipolar transistor characteristics from the p-channel tin oxide TFT is still unclear. The fabrication of highly transparent tin oxide thin film with bipolar transistor characteristics is demonstrated herein.

(Invited) Investigation of Critical Interfaces in Few-Layer MoS2 Field Effect Transistors with High-k Dielectrics

Transition metal dichalcogenides (TMDs) as 2D or few-layer semiconducting channel material are being widely studied to lower power consumption and obtain negligible short channel effects with continued transistor scaling [1-4]. Meanwhile, research needs to be conducted on top-gated, metal-oxide-semiconductor field effect transistors (MOSFETs) to correctly assess the possibility of TMDs supplanting silicon in the channel region. This is because top-gate device architectures face some key integration challenges that typical bottom-gate TMD FET structures do not experience. As an example, molybdenum disulfide (MoS2) is supposed to have no dangling interfacial bonds, making it difficult to form high-k dielectrics on them. Therefore, surface functionalization of TMDs has attracted attention [5-12]. However, detailed understanding on performance of transistors with metal/high-k/TMD top-gate stacks are still lacking. In addition, a major hurdle of incorporating these two-dimensional (2D) materials in device structures of any kind is the high contact resistance at the metal/TMD interface [13-15]. Recent results have shown that the backside dielectric can influence top-gate MOSFET performance [16]. In this work, few-layer MoS2 FET-based devices were fabricated using top and bottom high-k dielectrics (Al2O3 and/or HfO2). The C-V response of a top-gate, HfO2/MoS2 gate stack on a backside SiO2 layer demonstrated the existence of specific defects at the interface, which demonstrated frequency dependent “humps” in depletion – similar to conventional Si MOSFETs with unpassivated silicon dangling bonds in the dielectric/Si interfacial region. Also, a comparison of UHV and HV metal deposition on MoS2 as contacts for source and drain was done where results demonstrated that UHV deposited metals were superior to HV ones. In an additional experiment with Al2O3 as the bottom-gate dielectric layer, the intrinsic mobility and subthreshold slope were greatly improved compared to SiO2 or HfO2 as back gate dielectric FETs, indicating a positive influence on top-gate device performance even without any backside bias. Furthermore, a forming gas anneal is found to further enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation. Another significant finding in top-gate FET performance is the high-k dielectric screening effect of the backside Al2O3 layer. Results demonstrate that the extracted top-gate field effect mobility values are higher compared to SiO2 or HfO2 as a backside oxide – even though all FETs have the same top-side HfO2 dielectric oxide and no back bias. Acknowledgement – This work was supported in part by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, Science Foundation Ireland under the US-Ireland R&D Partnership Programme Grant Number SFI/13/US/I2862, and the center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA.

Electrode configurations for pentacene-deposited organic thin film transistors

ABSTRACTWhen a pentacene OTFT is fabricated with a bottom gate structure, the top-contact configuration of gold electrodes is preferred because it results in better electrical performance than the bottom-contact configuration. Pentacene molecules are deposited only on the SiO2 dielectric layer in the top-contact configuration, and thus all pentacene molecules form a vertical orientation that induces efficient charge transport between molecules. However, in an OTFT device with the bottom-contact configuration, pentacene molecules adopt a random tilted orientation at the boundary of the gold electrode, resulting in poor charge transport between molecules.

Effects of channel structure consisting of ZnO/Al2O3 multilayers on thin-film transistors fabricated by atomic layer deposition

By applying a novel active layer comprising ZnO/Al2O3 multilayers, we have successfully fabricated fully transparent high-performance thin-film transistors (TFTs) with a bottom gate structure by atomic layer deposition (ALD) at low temperature. The effects of various ZnO/Al2O3 multilayers were studied to improve the morphological and electrical properties of the devices. We found that the ZnO/Al2O3 multilayers have a significant impact on the performance of the TFTs, and that the TFTs with the ZnO/15-cycle Al2O3/ZnO structure exhibit superior performance with a low threshold voltage (VTH) of 0.9 V, a high saturation mobility (μsat) of 145 cm2 V−1 s−1, a steep subthreshold swing (SS) of 162 mV/decade, and a high Ion/Ioff ratio of 3.15 × 108. The enhanced electrical properties were explained by the improved crystalline nature of the channel layer and the passivation effect of the Al2O3 layer.

Direct graphene growth on transitional metal with solid carbon source and its converting into graphene/transitional metal oxide heterostructure

The oxide/semiconductor structure is key to controlling current in electronic devices and HfO2 is a common gate material in conventional electronic devices due to its favorable dielectric properties. Graphene devices also require insulating gates. We demonstrate a unique direct growth approach to obtain the bottom gate structure (graphene/HfO2/n-SiC). The present approach involves transfer of graphene grown by chemical vapor deposition (CVD) on Cu to oxidized Si wafers, a complex process prone to low yield and reduced performance. Furthermore, HfO2 is preferred to SiO2 because of its superior properties. The proposed concept consists of the direct deposition of graphene by solid carbon molecular beam epitaxy on Hf metal coated n-type SiC, followed by oxygen intercalation to form HfO2. The oxygen intercalation will then convert the underlying Hf into HfO2 due to the strong affinity of Hf with oxygen. We identify the graphene/HfO2 formation by Raman, X-ray photoelectron spectroscopy (XPS), Low energy electron diffraction (LEED), Low energy electron microscopy (LEEM) and electrical properties including Hall mobility and leakage current measurement.

Preparation and effects of post-annealing temperature on the electrical characteristics of Li–N co-doped ZnSnO thin film transistors

In this study, transparent Li–N co-doped ZnSnO (ZTO: (Li, N)) thin film transistors (TFTs) with a staggered bottom-gate structure were fabricated by radio frequency magnetron sputtering at room temperature. Emphasis was placed on investigating the effects of post-annealing temperature on their physical and electrical properties. An appropriate post-annealing temperature contributes not only to achieving good quality thin films, but also to improving the electrical performance of the ZTO: (Li, N) TFTs. The ZTO: (Li, N) TFTs annealed at 675°C showed the best electrical characteristics with a high saturation mobility of 26.8cm2V−1s−1, a threshold voltage of 6.0V and a large on/off current ratio of 4.5×107.

Self-aligned metal double-gate junctionless p-channel low-temperature polycrystalline-germanium thin-film transistor with thin germanium film on glass substrate

Low-temperature (LT) polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) are viable contenders for use in the backplanes of flat-panel displays and in systems-on-glass because of their superior electrical properties compared with silicon and oxide semiconductors. However, LT poly-Ge shows strong p-type characteristics. Therefore, it is not easy to reduce the leakage current using a single-gate structure such as a top-gate or bottom-gate structure. In this study, self-aligned planar metal double-gate p-channel junctionless LT poly-Ge TFTs are fabricated on a glass substrate using a 15-nm-thick solid-phase crystallized poly-Ge film and aluminum-induced lateral metallization source–drain regions (Al-LM-SD). A nominal field-effect mobility of 19 cm2 V−1 s−1 and an on/off ratio of 2 × 103 were obtained by optimizing the Al-LM-SD on a glass substrate through a simple, inexpensive LT process.

Fast Threshold Voltage Compensation AMOLED Pixel Circuit Using Secondary Gate Effect of Dual Gate a-IGZO TFTs

We report a fast threshold voltage ( $\text{V}_\mathrm {TH})$ compensation pixel circuit for active-matrix organic light-emitting diode displays. The circuit utilizes the secondary gate effect in amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) with the dual-gate (DG) (bottom and top gate) structure and consists of three single-gate TFTs, one DG driving TFT, and two capacitors. It compensates the initial $\text{V}_{\mathrm {TH}}$ variation after fabrication and takes into account the carrier mobility differences between the top and bottom channels of a DG TFT by using a correction TFT that enables $\text{V}_\mathrm {TH}$ sampling via the channel with the higher mobility, the bottom channel. This achieves very short $\text{V}_\mathrm {TH}$ sampling time, below $10~\mu \text{s}$ . Experimental results are consistent with those from Silvaco SmartSpice simulations.

Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing.

Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics.

Low-Temperature Growth of Indium Oxide Thin Film by Plasma-Enhanced Atomic Layer Deposition Using Liquid Dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium for High-Mobility Thin Film Transistor Application.

Low-temperature growth of In2O3 films was demonstrated at 70-250 °C by plasma-enhanced atomic layer deposition (PEALD) using a newly synthesized liquid indium precursor, dimethyl(N-ethoxy-2,2-dimethylcarboxylicpropanamide)indium (Me2In(EDPA)), and O2 plasma for application to high-mobility thin film transistors. Self-limiting In2O3 PEALD growth was observed with a saturated growth rate of approximately 0.053 nm/cycle in an ALD temperature window of 90-180 °C. As-deposited In2O3 films showed negligible residual impurity, film densities as high as 6.64-7.16 g/cm3, smooth surface morphology with a root-mean-square (RMS) roughness of approximately 0.2 nm, and semiconducting level carrier concentrations of 1017-1018 cm-3. Ultrathin In2O3 channel-based thin film transistors (TFTs) were fabricated in a coplanar bottom gate structure, and their electrical performances were evaluated. Because of the excellent quality of In2O3 films, superior electronic switching performances were achieved with high field effect mobilities of 28-30 and 16-19 cm2/V·s in the linear and saturation regimes, respectively. Furthermore, the fabricated TFTs showed excellent gate control characteristics in terms of subthreshold swing, hysteresis, and on/off current ratio. The low-temperature PEALD process for high-quality In2O3 films using the developed novel In precursor can be widely used in a variety of applications such as microelectronics, displays, energy devices, and sensors, especially at temperatures compatible with organic substrates.

Investigation on the Gate Electrode Configuration of IGZO TFTs for Improved Channel Control and Suppression of Bias-Stress Induced Instability

The classic bottom-gate IGZO TFT structure requires a passivation layer application over the back-channel for stability and process integration. However, the passivation material deposition process usually degrades the interface quality and presents defect states at the back-channel interface which are difficult to compensate by a controlling gate electrode positioned on the opposite side of the semiconductor. A top-gate configuration takes advantage of a superior back-channel interface between the substrate and the sputtered IGZO film. The gate dielectric must be deposited on the IGZO which presents an inferior interface, however the influence of defect states can be reduced by annealing in an oxidizing ambient prior to the gate electrode deposition. As positioned directly above the inferior interface, there is an improvement in the ability of the gate potential to control the device operation in the presence of remaining defect states. This work presents an investigation on TFTs which have been fabricated with very similar process flows with the exception of the placement of the gate electrode. Bottom-gate TFTs with back-channel passivation that demonstrate good performance and resistance to aging have been realized, however bias-stress stability continues to remain a challenge. Top-gate TFTs have demonstrated improvement in the uniformity of device operation as well as bias-stress stability, and have the potential to offer an advantage in off-state performance (see fig. 1). Double-gate TFTs take further advantage of improved electrostatics, but present additional challenges in process integration. Results from all three gate electrode configurations will be compared. Device testing performed over a temperature range from 10 K to 400 K allows a comprehensive assessment of transport behavior (see fig. 2), with results used to refine a material and device model for TCAD simulation. Figure 1

Bottom-Gate Self-Aligned Homojunction TFT with Double Oxide Semiconducting Layers

After huge effort has been made over the last decade, oxide thin-film transistors (TFTs) have been successfully adopted in the backplane of high resolution AM-LCD and AM-OLED displays. However, as displays and electronic devices evolve to next generations, it is necessary to not only enhance field-effect mobility, but also reduce RC-delay for high driving speed [1, 2]. In this regard, self-aligned structure has been considered as one of promising candidates for satisfying these requirements [3] due to the minimum parasitic capacitances between electrodes. Nonetheless, there are several concerns especially in doping process at contact region because it is difficult to control dopant diffusion, resulting in unstable performance and another unexpected parasitic capacitance. Here, we propose improved structure adopting double oxide semiconducting layers, which can precisely define the channel dimension by gate electrode. Figure 1 demonstrates both structures of conventional self-aligned TFT and our improved self-aligned TFT. As shown in the figure, first channel layer of oxide material with high mobility and high carrier density plays as the real electron flow path and the contacts with source/drain (S/D) metal electrode without additional doping process. Consequently, the issues originated from doping process can be easily overcome. Meanwhile, second active layer with the relatively low carrier density is defined by the gate electrode and plays a role as a carrier controlling part for reliable switching performance. To fabricate our self-aligned TFTs, gate metal was firstly patterned on glass substrate by wet etching. After depositing SiO2 by PECVD as a gate insulator, first semiconducting layer was grown by sputter or plasma-enhanced atomic layer deposition (PEALD). The second active layer was deposited and formed by back-side exposure using gate electrode as a masking layer. Then, SiO2 by PECVD was deposited to passivate whole device. Finally, S/D metal layer was formed, followed by annealing process in vacuum condition. As a starting research, we had to carefully consider proper oxide semiconductors according to their characteristics and etch selectivity between first and second channel layers. Although adopting highly conducting oxides such as ITO and In2O3 as a first channel layer would be better for lowering the contact resistance, it is hard to deplete the carriers. Hence, thinner film thickness (<10nm) or other deposition method such as PEALD should be considered to obtain semiconducting behavior. Accordingly, we have firstly investigated the switching behavior of In2O3/ZnO double layered TFT by means of PEALD with bottom-gate coplanar structure. The In2O3/ZnO TFT shows mobility of 32 cm2/Vs with good bias stability as shown in Figure 2. The improved self-aligned TFTs were successfully fabricated and well-performed using sputtered ITO/IGZO and PEALD In2O3/ZnO. We will report the device characteristics and further investigate and reveal the origin of stable electrical behavior by simulation. [Acknowledgement] This work was supported by Open Innovation Lab Project from National Nanofab Center (NNFC). [Reference] [1] K. Yokoyama, S. Hirakata, S. Yamazaki, M. Nakada, T. Sato, and N. Goto, “A 2.78-in 1058-ppi ultra-high-resolution OLED display using CAAC-OS FETs,” SID digest 2015, 46, 1039-1042. [2] J. U. Bae, D. H. Kim, K. Kim, K. Jung, W. Shin, I. Kang, and S. D. Yeo, “Development of oxide TFT’s structures,” SID digest 2013, 44, 89-92. [3] N. Morosawa, Y. Ohshima, M. Morooka, T. Arai, and T. Sasaoka, “Novel self-aligned top-gate oxide TFT for AMOLED displays,” Journal of the society for Information Display 2012, 20 (1), 47-52. Figure 1

High Photoresponsivity Multilayer MoS2 Thin-Film Transistors with Local Bottom Gate Structure

2D layered transition metal dichalcogenides (TMDs), especially MoS2, has received great attention for next-generation semiconductor devices because their thin film transistors (TFTs) show a nearly ideal subthreshold swing (SS ≈ 70 mV decade-1), high on/off current ratio (I on/I off ≈ 108), and high field-effect mobility (µ eff > 100 cm2 V-1 s-1). In addition, TMDs have the optical characteristic of tuning bandgap from direct to indirect with increasing their layers. Even though photoresponsivity of multilayer MoS2 phototransistor due to its nature of indirect bandgap is lower than that of single layer MoS2, multilayer MoS2 has higher density-of-state and wider spectral response than single layer MoS2. In order to enhance photoresponsivity of multilayer MoS2 phototransistor, we suggest the phototransistor with local bottom gate structure (LBGS), where the bottom gate length of the device is shorter than the channel length. The underlap regions of between gate and channel work like the series resistance in dark state due to ineffective gate modulation at the region. To demonstrate the enhancement of phototransistor performance using LBGS, we previously studied amorphous silicon TFT with LBGS. The photosensitivity enhancement up to 64 times as compared to the conventional a-Si TFT. And then, we used multilayer MoS2 as a channel material to constitute phototransistor with LBGS. The giant photoreponsivity of 342.6 AW-1 at 2 mW cm-1 shows three orders of magnitude larger than that of global gate multilayer MoS2 TFTs. This result of our experiment and simulation reveals that multilayer MoS2 phototransistor with local bottom gate can be used as various photosensing devices.