Bottom Junction Research Articles

Low-temperature characteristics of well-type guard rings in epitaxial CMOS

Characterization and simulation of minority-carrier well-type guard rings in epitaxial substrate at 77 K were performed and compared with those at RT. The escape probability in a narrow guard-ring structure under the same amount of minority carrier injection increases by about one order of magnitude when temperature decreases to 77 K. This degradation in the guard-ring efficiency can be attributed to the enhanced drift mechanism in the conductivity-modulated layer between the well bottom junction and the epitaxial high/low junction at 77 K. In contrast, this mechanism enhances the width dependence of the escape probability at 77 K. The higher minority-carrier recombination velocity of the epitaxial high-low junction contributes to the stronger width dependence secondarily. When the epitaxial layer thickness becomes thinner, the simulation also demonstrates a stronger width dependence of the escape current as well as a reduction in its magnitude. A lightly-doped epitaxial layer on a heavily-doped substrate exhibits even more importance in the guard ring efficiency for low temperature operation, and its thickness should be kept as thin as possible.

Stress Distribution and Mass Transport Along Grain Boundaries During Steady-State Electromigration

ABSTRACTStress distribution and mass flux in the plane of each grain boundary within a polycrystalline thin-film conductor have been calculated during electromigration for zero flux divergence (steady state) and various boundary conditions. Steady state, representing a balance between the (applied) electric and (induced) stress driving forces, is assumed to develop after a short transient time. Boundary conditions at the intersection of grain boundaries with the top and bottom conductor surfaces (surface junctions) and with the conductor edges (edge junctions) are assumed to be of two types: open (flux passes freely) and closed (zero flux). Flux is assumed to pass freely at the intersection of grain boundaries with each other (triple Junctions). Several grain boundary configurations are considered, including individual boundaries, single triple junctions, and combinations thereof, assuming that bottom surface junctions (conductor/ substrate interface) are closed and that top surface junctions are either open (bare conductor) or closed (passivation layer). Results clearly show the formation of incipient holes and hillocks near the intersection of triple junctions and/or closed (blocked) edge junctions with open surface junctions.

Charge collection spectroscopy

Monitoring pulses measured between the power pins of a microelectronic device exposed to high LET (linear energy transfer) ions yields important information on the SEU (single event upset) response of the circuit. Analysis of p-well CMOS devices is complicated by the possibility of competition between junctions, but the results suggest that charge collection measurements are still sufficient to determine SEU parameters accurately. It is shown that the charge collection obtained off the power lines of a p-well CMOS device can be explained if one takes into account the fact that the well-substrate and source-well junctions compete for the diffusion charge. To produce a pulse that lies within the peak, the ion must cross the top and bottom junctions of the sensitive volume. The first-order model remains a valid approximation of the complicated charge collection mechanisms that occur when an ion strikes each of the junctions. A comparison of experimental data with the new theories is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Spectral response measurements of two-terminal triple-junction a-Si solar cells

A method of measuring the spectral response of each component junction in a two-terminal triple-junction a-Si solar cell has been developed. The method uses a white bias light and off-the-shelf optical interference filters selected to reduce the bias light encountering each component junction. The a-Si top junction is measured when the cell is biased with wavelengths of 585–1100 nm, the a-Si middle junction is measured when the cell is biased with wavelengths of 350–505 nm and 795–1100 nm and the a-SiGe bottom junction is measured when the cell is biased with wavelengths of 380–670 nm. In turn, the chopped light from a monochromator is used to measure the spectral response of the low-biased junctions. Spectral response curves of the Solarex a-Si/a-Si/a-SiGe triple junction solar cell are presented. In addition, the AMO Isc (short circuit current) of this individual cell type is confirmed to be within ±2% of the Isc obtained when the spectral response of the current limiting junction is integrated with either the AM0 spectral irradiance or that of a closely matched (±10% from 350 nm to 900 nm) X-25 Mark II solar simulator.

Analytical design formulation for minority-carrier well-type guard rings in CMOS circuits

Minority carriers injected from an active emitter into the substrate and partially collected by the bottom well junction in an epitaxial CMOS structure are studied. Two-dimensional numerical simulation has revealed that the minority-carrier collection current along the bottom well junction is contributed primarily by two mechanisms: the first due to minority carriers injected into a layer between the upper collecting plate and the bottom reflecting plate; and the second due to those penetrating the high/low junction and then spreading out in the large, highly-doped bulk as in the nonepitaxial case. Based on this observation, a new analytic model for the minority-carrier escape current has been developed as a measure of well-type guard ring efficiency. This model, including a closed-form expression as function of epitaxial layer thickness, well junction depth and guard ring width, has been confirmed by experimental data as well as by two-dimensional numerical simulation. As predicted by the model, the measured escape current has been found to be dominated by the second mechanism for the case of well junction depth close to epitaxial layer thickness while the first mechanism has been identified to dominate the escape current measured from the structure having sufficient epitaxial layer thicknesses.

Review of progress on a-Si alloy solar cell research

Abstract Materials and device studies have focused on the development of a-SiGe:H and a-SiC alloys for high performance multijunction solar cells and submodules. Outdoor measurements of a-SiC:H/a-Si:H/a-SiGe:H cells have yielded 10.7% conversion efficiency for a triple junction cell which contained a 1.4 eV bandgap bottom cell. a-SiC/a-SiGe submodules with a 2500 A thick bottom junction have shown efficiencies as high as 7.7% (active area 900 cm2) and single junction submodules have yielded a conversion efficiency of 9.8%. Stacked junction devices show a clear improvement in stability, compared to equivalent single junction devices. Tandem junction devices with a conversion efficiency of 9% have been prepared which exhibit only an 11% performance loss after 1000 hours continuous AM 1.5 illumination at 40 °C. Analysis indicates that the net degradation of a stacked device is the mean of the component single junction devices. p-Layers prepared from B(CH3) have been extensively studied. The optical bandgap of the p-layer increases by approximately 0.1 eV at a given value of conductivity compared to films prepared from diborane. Devices prepared from the feedstock have shown open circuit voltages as high as 0.943 and fill factors as high as 0.74 and unoptimized devices with an efficiency of 11.5% have been measured. In contrast microcrystalline alloys show little or no improvement in open circuit voltages. The steady state photocarrier grating (SSPG), photoconductivity and photothermal defection spectrometry have been used to understand and improve the properties of a-SiGe:H films prepared using a wide variety of feedstocks and deposition conditions. Studies have shown that trace levels of boron have a marked influence on the ambipolar diffusion length of both a-SiGe:H and a-Si:H films. In single chamber systems boron doping occurs due to carryover from the p-layer deposition.

Properties of stacked NbN tunnel junctions

Stacks of up to three tunnel junctions were fabricated using the NbN-MgO technique. Different preparation methods were tested, and two gave favorable results. In the first one, the whole stack is prepared in situ and structured afterwards by lift-off and reactive and argon ion etching. The authors investigated the resulting I-V (current-voltage) characteristics of stacks of 8.3 mV. Since it was not possible to establish electrical connections to the intermediate electrodes by this method, a second one was applied in which each NbN/MgO layer is prepared in a separate step and structured by lift-off. Here the I-V characteristics, the interaction between the tunnel junctions, and their RF properties were investigated. Shapiro steps and photon-assisted tunneling were observed in the I-V characteristics of a receiver junction, while the bottom tunnel junctions were used as microwave generators. >

A-Si Basis Heterojunction Stacked Solar Cells

ABSTRACTA systematic study has been made on a-Si basis heterojunction tandem structure solar cells. Design rule and optimizations of cell parameters on two and three stacked heterojunction solar cells are discussed on various material bottom junctions stacked with a-Si. A series of experimental trials has been made on some candidate materials. Technical data on cell fabrication processes, device performance are presented. In the -present stage of experiments, 13.3% efficiency on a-Si/poly-Si two terminals tandem solar cell and also on a-Si//poly- CdS/CdTe four terminals cell have been obtained. Some key technologies for future low cost massproduction processes such as growth of polycrystalline thin film for bottom cell are also discussed.

The lateral p-n-p transistor—A practical investigation of the DC characteristics

The dc characteristics of the lateral p-n-p transistor are investigated with the goal of providing an uncomplicated but accurate description that considers the practical needs of the device and circuit designer. An experimental step-by-step analysis of collector- and base-current components shows that a one-dimensional model describes the device adequately. The model parameters are closely related to process parameters and device geometry allowing quick assessments of layouts and processes. In particular, a comparison of various emitter geometries is given, showing among other facts the adverse effect of unnecessarily large emitter contact holes. Of the mechanisms determining the base current, volume and surface recombination in the intrinsic base were found to be insignificant. Instead, an additional component, the vertical diffusion of holes out of the intrinsic base, has been experimentally verified. The main contribution to base current, however, is the current across the emitter bottom junction. High-level injection is considered in the collector current by using a modification of Chou's equations. Gummel-Poon knee voltages have been determined for various dopings and basewidths. Our experiments show that the knee voltage depends on basewidth, which goes beyond Chou's description.

An investigation of the intrinsic delay (speed limit) in MTL/I/sup 2/L

Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. The injection model is used, into which new charge storage parameters are introduced. The majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. A device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.

An investigation of the intrinsic delay (speed limit) in MTL/I2L

This paper identifies and analyzes the main mechanisms that determine the intrinsic delay (speed limit) of today's MTL/I2L devices. Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. Hereby, the injection model is used, into which new charge storage parameters are introduced. According to the analysis, the majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high-level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. Using the insight gained, a device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.

“The Old Woman in the Shoe”

The primary objective of this modeling investigation is to optimize a multijunction tandem device under the AM1.5G spectrum. Based on previous studies, InP and Ge cells, because of their energy band gaps, can be combined together to achieve high-efficiency double-junction devices. In this study, the top cell is made of InP (1.35 eV) while the bottom cell is made of Ge (0.66 eV). In order to avoid the losses and design constraints observed in two-terminal and four-terminal devices.In order to determine the optimal structure of the device, the top and bottom junctions were investigated and optimized with regard to the thicknesses. The optimum configuration of the device shows an efficiency of 26.79% under the AM1.5G spectrum and one sun, which is higher than the efficiency of an optimized single-junction Si cell under the same illumination conditions.