Abstract
Monitoring pulses measured between the power pins of a microelectronic device exposed to high LET (linear energy transfer) ions yields important information on the SEU (single event upset) response of the circuit. Analysis of p-well CMOS devices is complicated by the possibility of competition between junctions, but the results suggest that charge collection measurements are still sufficient to determine SEU parameters accurately. It is shown that the charge collection obtained off the power lines of a p-well CMOS device can be explained if one takes into account the fact that the well-substrate and source-well junctions compete for the diffusion charge. To produce a pulse that lies within the peak, the ion must cross the top and bottom junctions of the sensitive volume. The first-order model remains a valid approximation of the complicated charge collection mechanisms that occur when an ion strikes each of the junctions. A comparison of experimental data with the new theories is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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