Bond Pad Research Articles

Flexible and Extensible Ribbon-Cable Interconnects for Implantable Electrical Neural Interfaces.

The design and characterization of thin-film ribbon cables as electrical interconnects for implanted neural stimulation and recording devices are reported. Our goal is to develop flexible and extensible ribbon cables that integrate with thin-film, cortical penetrating microelectrode arrays (MEAs). Amorphous silicon carbide (a-SiC) and polyimide were employed as the structural elements of the ribbon cables and multilayer titanium/gold thin films as electrical traces. Using photolithography and thin-film processing, ribbon cables with linear and serpentine electrical traces were investigated. A cable design with an open lattice geometry was also investigated as a means of achieving high levels of extensibility while preserving the electrical function of the cables. Multichannel ribbon cables were fabricated with 50 mm lengths and metallization trace widths of 2-12 μm. The ribbon cables tolerate flexural bending to a radius of 50 μm with no change in trace impedance but tolerate less than 5% tensile elongation without trace failure. Ribbon cables with a lattice structure exhibit 300% elongation without failure. The high elongation tolerance is attributed to a lattice design that results in an out-of-plane displacement that avoids fracture or plastic deformation. Extensible ribbon cables underwent up to 50,000 tensile elongation cycles to 45% extension without failure. An electrical interconnect process using through-holes in the distal gold bond pads of the ribbon cables was used to connect to an a-SiC-based MEA. The electrical connection was created by stenciling a conductive epoxy into the through-holes, bridging metallization between the traces, and MEA. The interconnect was tested using a ribbon cable connected to an a-SiC MEA implanted acutely in rat cortex and used to record neuronal activity. These highly flexible and extensible ribbon cables are expected to accommodate large extensions and facilitate cable routing during surgical implantation. They may also reduce tethering forces on implanted electrode arrays, potentially improving chronic neural recording performance.

On Legalization of Die Bonding Bumps and Pads for 3-D ICs

On Legalization of Die Bonding Bumps and Pads for 3-D ICs

Influence of Solder Mask on Electrochemical Migration on Printed Circuit Boards.

Electrochemical migration (ECM) on the surface of printed circuit boards (PCBs) continues to pose a significant reliability risk in electronics. Nevertheless, the existing literature lacks studies that address the solder mask and solder pad design aspects in the context of ECM. Therefore, the objective of this study was to assess the impact of solder mask type with varying roughness and solder pad design on the susceptibility to ECM using a water drop test and thermal humidity bias test. Hot air solder leveling-coated PCBs were tested. Furthermore, the ECM tests were conducted on PCBs with applied no-clean solder paste to evaluate the influence of flux residues on the resulting ECM behavior. The results indicated that the higher roughness of the solder mask significantly contributes to ECM inhibition through the creation of a mechanical barrier for the dendrites. Furthermore, lower ECM susceptibility was also observed for copper-defined pads, where a similar effect is presumed. However, the influence of the no-clean flux residues can prevail over the effects of the solder mask. Therefore, the use of a rough solder mask and a copper-defined pad design is recommended if the PCB is to be washed from flux residues after the soldering process.

Functional performance of low-cost electronic yarn for E-textiles

The current work presents and discusses the design and performance qualities of braided electronic yarns for woven textiles to produce red light-intensity effects. The design process involves a simple encapsulation process with adhesive tape and a heat-shrinkable tube to secure stainless-steel conductive threads (SS-CTs) to the solder pads of light-emitting diodes. These are arranged in a series against two SS-CTs to provide single positive and negative terminals at both ends. Findings from the infrared images show that the heat distribution and dissipation of the stainless-steel conductive threads are insignificant in affecting the wear comfort of the electronic textiles on the human body. The washing test shows the robust nature of the braided electronic yarns even after 20 cycles of being subjected to high agitation and mechanical stress. A proof of concept illustrates the effectiveness of the study results, which calls on further research work to enhance the durability and flexibility of the braided electronic yarns and electronic textiles to ensure a higher level of wear comfort. These braided electronic yarns would find end applications for nighttime visibility of pedestrians, a situation that would improve the recognition of drivers for reduced collision.Graphical abstractA simple low-cost process to manufacture electronic yarns (e-yarns) starts by embedding light-emitting diodes (LEDs) in series on two stainless-steel conductive threads (SS-CTs) through encapsulation in a heat-shrinkable tube (HST), and insulating one side of the SS-CT, then braided by using 8-core retroreflective threads that are then woven to form an electronic textile (e-textile). The braided e-yarns and e-textiles when washed exhibit good performance properties for clothing that would be interactive to enhance the nighttime visibility of pedestrians.Impact statementElectronic textiles otherwise known as e-textiles have been the subject of scholarly attention in recent years due to their performance properties and wide areas of application for entertainment, monitoring, and safety purposes. The use of appropriate electronic yarns (e-yarns) plays a key role in connectivity and provides the necessary feedback when applied to a textile material. E-yarns are now replacing a few modern electronic textiles (e-textiles) that use rigid copper wires commonly applied in electronic circuits for e-textiles and improve the wear comfort of the garment. The integration of light-emitting diodes (LEDs) into conductive threads to form electronic yarns for textile material can be applied not only for entertainment purposes but also as a safety feature for pedestrians. The use of appropriate components is necessary to ensure and maintain the textile quality and properties for effective wearability. Herein, an e-yarn fabricated with stainless-steel conductive threads and LEDs for e-textiles is presented. As part of ongoing research work to develop smart interactive clothing to increase the nighttime visibility of pedestrians, this work discusses the design and performance qualities of braided e-yarns for woven textiles. The success of these low-cost, flexible, and strong (high wash durability) braided e-yarns facilitates their integration into woven fabrics for smart clothing to enhance the visibility and therefore safety of pedestrians.

Contact Resistivity of Submicron Hybrid Bonding Pads Down to 400 nm

Contact Resistivity of Submicron Hybrid Bonding Pads Down to 400 nm

Random Vibration Fatigue Life Prediction of Nano-Silver Solder Joint

Nano-silver is a very potential electronic interconnection material. It’s excellent physical and chemical properties, high thermal conductivity and good electrical conductivity make it very suitable for high power electronic devices. In practical engineering, 20% of the failure of electronic products is caused by vibration load, so it is necessary to study the vibration reliability of interconnected materials. In this paper, the modal and random vibration finite element analysis of nano-silver solder joints were analyzed with workbench software. Predicting random vibration fatigue life of nano-silver solder joint by Coffin-Manson high cycle fatigue empirical formula, Miner’s linear cumulative damage theory and Steinberg model. The random vibration fatigue life of the nanosilver solder joint is 8342 h. It is found that the vibration reliability of nano-silver is inferior to Sn3.0Ag0.5Cu and Sn63Pb37 and the diameter of solder joints and PCB thickness are proportional to the vibration fatigue life, and the PCB thickness has a greater effect on the vibration life than the solder joint diameter. Solder joint height and pad thickness are inversely proportional to vibration fatigue life, and pad thickness has little effect on vibration fatigue life.

Effect of solder void on mechanical and thermal properties of flip-chip light-emitting diode: Statistical analysis based on finite element modeling

With the increasing demand for highly efficient lighting in the automotive industry, flip-chip light-emitting diodes (LEDs) have become widely used for both interior and exterior lighting. Solder, serving as a crucial interconnecting material, often develops voids during the reflow process, compromising the integrity and reliability of the connections. Thus, understanding the impact of these voids on the mechanical and thermal properties of the product is vital for improving reliability accuracy. This work employs computational methods alongside experimental approaches to address the challenges of replicating solder voids and controlling the solder void fraction. A comprehensive study investigates the effects of solder voids on shearing properties and thermal conductance. Random voids were introduced into the solder pads of an LED assembly within a finite element model (FEM), leading to predictions of maximum shear stress and LED junction temperature. The findings correlate well with the experimental data, validating the FEM's applicability. Furthermore, a statistical analysis was conducted to explore the relationship between solder void fraction, position, and size, aiming to provide objective guidelines for analyzing soldered assembly tomography in reliability assessments.

Effects of Pd Alloying and Coating on the Galvanic Corrosion between Cu Wire and Bond Pads for a Semiconductor Packaging

Semiconductor chips are packaged in a process that involves creating a path to allow for signals to be exchanged with the outside world and ultimately achieving a form to protect against various external environmental conditions such as heat and moisture. The wire bonding type of packaging is a method in which thin metal wires are bonded to pads to create an electrical connection between the chip and the lead frame. An Epoxy Molding Compound (EMC) can be applied to protect semiconductor chips from external environmental conditions such as heat, shock, and moisture. However, EMC contains halogen elements and sulfides and has hydrophilic properties, which can lead to a corrosive environment. The present study aims to evaluate the influence of chloride, which is a contaminant formed during the PCB manufacturing process. To this end, the galvanic corrosion of bonding wire materials Cu wire, Cu wire alloyed with 1% Pd, and Cu wire coated with Pd was investigated. The first ball bond was bonded to the Al pad and the second stitch bond was bonded to the Au pad of the manufacturing process, after which the galvanic corrosion behavior in the semiconductor packaging module specimen was analyzed. A model of galvanic corrosion behavior was also proposed.

Development and Improvement of a Piezoelectrically Driven Miniature Robot.

In this paper, we proposed a miniature quadrupedal piezoelectric robot with a mass of 1.8 g and a body length of 4.6 cm. The robot adopts a novel spatial parallel mechanism as its transmission. Each leg of the robot has two degrees of freedom (DOFs): swing and lift. The trajectory necessary for walking is achieved by the appropriate phasing of these two DOFs. A new manufacturing method for piezoelectric actuators was developed. During the stacking process, discrete patterned PZT pieces are used to avoid dielectric failure caused by laser cutting. Copper-clad FR-4 is used as the solder pad instead of copper foil, making the connection between the pad and the actuator more reliable. The lift powertrain of the robot was modeled and the link length of the powertrain was optimized based on the model. The maximum output force of each leg can reach 26 mN under optimized design parameters, which is 1.38 times the required force for successful walking. The frequency response of the powertrain was measured and fitted to the second-order system, which enabled increased leg amplitudes near the powertrain resonance of approximately 70 Hz with adjusted drive signals. The maximum speed of the robot without load reached 48.66 cm/s (10.58 body lengths per second) and the payload capacity can reach 5.5 g (3.05 times its mass) near the powertrain resonance.

Effect of Conformal Coating on Electrochemical Migration Behavior of Multi-Layer Ceramic Capacitor for Automotives Based on Water Drop Test

A large amount of multi-layer ceramic capacitor (MLCC) is mounted inside a printed circuit board (PCB) constituting electronic components. The use of MLCC in electric vehicles and the latest mobile phones is rapidly increasing with the latest technology. Environments in which electronic components are used are becoming more diverse and conformal coatings are being applied to protect mounted components from these environments. In particular, MLCCs in electronic components mainly have voltage applied. They might be used in environments where humidity exists for various reasons. In a humid environment, electrochemical migration (ECM) will occur, with the cathode and anode on the surface of the MLCC encountering each other. This can result in product damage due to a short circuit. In this study, the effects of voltage, NaCl concentration, and distance between electrodes on a non-mount MLCC, surface mount MLCC, and solder pad pattern were evaluated using a water drop test (WDT). Based on the analysis of the effects of the presence of conformal coating, applied voltage, concentration of NaCl, and the distance between electrodes, a mechanism model for ECM behavior in MLCCs was proposed.

Numerical investigation of solder joint shape for micro-spring package during vacuum vapor phase soldering

The novel micro-coil spring package has become a new choice for reliable applications in extreme temperature change, high-strength impact, long-term vibration and other harsh environments due to the advantages arising from its special packaging design. The study of solder joint shape is an important step in the characterization of the package reliability. By Ansys Fluent software, the finite volume method was applied to investigate the flow behavior of molten solder during vacuum vapor phase soldering and the volume of fluid model was used to track the solder melt front. The simulation results reveal the effect of two critical process parameters (solder volume and pad diameter) on solder joint shape in micro-spring array package. The fillet height of the solder joint increases with decreasing pad diameter and decreases with decreasing solder volume. The optimal solder volume is 0.07 mm3 coupled a pad diameter of 0.80 mm, producing suitable fillet height and nice concave fillet shape, which is in agreement with the real sample of micro-spring soldering joint. The good consistency between experiment and simulation proves that the finite element method can effectively predict the shape of the melted solder. This work paves the way for the optimization of the solder joint shape in the electronic assembly.

Insights into dynamic switching behavior and electric field distribution of depletion-mode GaN HEMT with bonding pad over active layout

Bonding pad over active (BPOA) layout, which stacks traditional horizontal structure pad electrodes vertically above the active area, is an area-effective device architecture and packaging-enabled solution for GaN-based high electron mobility transistors (HEMTs). In this work, the dynamic switching and electric field distribution of such layout, as well as associated capacitance–voltage and trapping characteristics, are comprehensively studied on D-mode GaN-on-sapphire HEMT by performing numerical simulations. In terms of different pad electrodes covering the active area, BPOA is composed of various structures such as gate-related and drain-related BPOAs (i.e. G-BPOA and D-BPOA), among which G-BPOA exhibits inferior switching characteristics due to the additional introduction of Miller capacitance that prolongs the device switching, while breakdown voltage of D-BPOA is 400–900 V lower than other BPOA counterparts due to the interplay between D-BPOA and the drain electrode. Furthermore, the effects of trap capture cross section and trap density on switching characteristics are evaluated. These results highlight the differences in electrical characteristics of various structures within the BPOA layout, and provide valuable insights into BPOA device design and performance improvement.

Hybrid Bonding for Ultra-High-Density Interconnect

Abstract Hybrid bonding is the technology for interchip ultrahigh-density interconnect at pitch smaller than 10 μm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub-0.5 μm has been demonstrated with scaling limitations under exploration beyond sub-0.4 μm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly overviewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing singulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.

Exploration of Interfacial Materials Chemistry Control to Improve Cu Wire Bonding Reliability

Copper wire bonding, with its advantages of higher electrical conductivity and better mechanical strength, has replaced gold wire bonding as a proven cost-effective electrical interconnection solution for IC packaging for the past 15 years. Early development of Cu wire bonding required overcoming of several technical challenges including bond pad damage caused by copper’s hardness and brittleness relative to gold. A more chemistry related challenge of using Cu as bonding wire is its well-known reactivity with oxygen. Inert atmospheric envelope of forming gas surrounding bonding capillary was developed to prevent oxidation of Cu wire during electronic flame off to enable a strong bonding. Another more elusive materials-chemistry related reliability challenge, with a typical low ppm occurrence, has been the chloride-induced corrosion defects between the Cu wire and Al bond pad. The opportunistic low-level chloride contaminations can originate from various points of packaging manufacturing process flow and often render it un-trackable. In this talk, we present recent efforts to systematically control interfacial materials chemistry across Cu bonding wire, Cu/Al bimetallic contacts and CuxAly intermetallic compounds with the aim to eliminate corrosion defects and improve the overall bonding reliability. The current prevailing manufacturing solution is to utilize Pd-coated Cu bonding wire that can only partially mitigate the CuxAly intermetallic corrosion vulnerability. We utilized a real-time corrosion screening metrology to explore the underlying interfacial materials chemistry drives vigorous corrosion between Cu wire and Al bond pad when exposed to trace level of chloride contaminant. Combining with SEM, sensitive infrared spectroscopy and electrochemical characterization, our data show strategic surface modification on both Cu bonding wire and exposed CuxAly intermetallic can have a significant impact on reducing corrosion defect rates. The obtained mechanistic insights provide several new strategies enabled by a novel Cu-selective passivation coating technology to effectively mitigate Cu wire bonding corrosion defects. Implications on further improving overall Cu wire bonding reliability will be present based on these new approaches that have low-cost and packaging friendly advantages.

Gold Coated Silver Bonding Wire and Its Consistent Reliability Performances

Thermal aging of gold coated silver bonded ball with aluminium bond pads exhibited a stable interface without Kirkendall voids until 4000h at 200°C for an un-molded device tested under vacuum. Ball and stitch pull remains in strength and remained constant until 4000 hours of aging. The growth of aluminides at the bond interface is about 4.5µm for 4000 hours of aging. The electrical resistance of the bonded ball remains the same until 4000 hours at 175°C for an epoxy molded device, molded with 5 to 7 pH green epoxy molding compound containing low chlorine and sulfur. Interestingly, the bonded ball interface of epoxy molded device has sustained 480h on biased Highly Accelerated Stress Test (bHAST) at +20V bias, 130°C, 85%RH. The bonded ball interface is stable until 1000 hours on unbiased HAST (uHAST) at 130°C, 85% RH as well. Cross-sectional ovservations of the bonded balls revealed the presence of intermetallic phases at the bond interface. However, formation of Kirkendall voids or crack propagatioon due to galvanic corrosions are absent.

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

Chemical mechanical polishing for indium bond pad damascene processing

We investigated chemical mechanical polishing (CMP) of indium, with the goal of obtaining indium bond pads for later cryo-3D integration of quantum computing-related chips, through bonding between these bond pads and indium bumps. Higher removal rates were obtained with soft CMP pads than with hard pads. The latter led to deep scratching, while this effect was much more limited for soft pad CMP. On patterned wafers, indium is cleared well in structured areas using soft pad CMP, leading to relatively high-quality indium surfaces inside bond pads, although corrosion might be of some concern. Pattern density uniformity was an important factor for within-die deviation in indium clearing time. Dishing was much more limited than in earlier work on indium polishing, while surface roughness was also found to be relatively limited. The obtained indium damascene bond pads may be suitable for 3D die-to-die and wafer-to-wafer bonding through indium pad-to-bump bonding.

Thermal Misfit and Diffusion Induced Stresses of Cu-Al Intermetallics in Microelectronics Wire Bonding

The thermosonic bonding technique is a widely used method for Cu wire interconnections. However, issues arise due to volumetric changes in intermetallic compounds (IMCs) formed at the Cu-Al bonding interface, leading to voids in the Cu-Al IMC layer. This problem is exacerbated after annealing, such as in high-temperature Storage (HTS). In this study, a statistical modelling approach was employed to quantitatively analyse stress, studying the evolution and characteristics of the interfacial microstructure in the thermosonic Cu wire-Al bond pad system. Microstructural analysis focused on Cu-Al IMC crystallography and compositional classification. A stress model was proposed, considering both thermal misfit and diffusion-induced stresses. Results showed that interfacial stress generally increased with higher bonding temperatures. The influence of forming gas supply was relatively minor, with oxide layers minimally impeding Cu-Al interdiffusion during Cu-Al IMC formation. This stress modelling technique hold potential as a valuable failure analysis tool for implementing Cu wire in various industries.

A practical ball‐grid‐array transition modelling methodology for accurate and fast multi‐interposer package simulation

AbstractAn equivalent circuit modelling methodology for the ball‐grid‐array (BGA) transition is proposed and validated with full‐wave electromagnetic simulation and measurement results. The BGA transitions modelled with the proposed methodology are validated to have a good accuracy up to 40 GHz. Unlike the existing BGA modelling methodologies which cannot model the BGA transition with short transmission lines within the anti‐pad region, the proposed methodology is developed from the practical BGA modelling scenario and models the irregular‐shape solder pads with transmission lines within the anti‐pad region. The BGA transitions modelled with the proposed methodology can be used for accurate and fast signal integrity simulations, analyses, and optimizations on 2.5D and 3D packaging. Additionally, factors impacting the accuracy of the equivalent circuit model are revealed by the proposed methodology.

Localization of Defects on PCBs with Diverse Acquisitions

The Printed Circuit Board (PCB) accommodates various Integrated Circuit (IC) components arranged in a specific layout of bond pads, lines, and tracks. Throughout the manufacturing process, irregularities or defects often occur during drilling, etching, stripping, and other stages, impacting the performance and functionality of the circuit board. Many of these defects are related to soldering pads and copper balance, identifying them through manual inspection is time-consuming and error-prone. This necessitates the use of Automated Optical Inspection (AOI). Practices like template matching often require two identical PCBs, which are compared using mathematical algorithms to detect differences. However, they are not resilient to viewpoint variations and non-rigid deformations. The current inspection process primarily focuses on rectifying PCB images captured with tilts ranging from 0 to 84 using homography principles. This correction process operates within a maximum run time of 7.96 s. The adjusted images then undergo analysis via a pattern-matching unit, where the system receives images of the same PCB pattern, each exhibiting different defects. Structural information mapping is performed using various spatial-domain feature-based matching algorithms. When evaluated using SSI and MSE metrics, the model achieved high matching percentages of 99.67%, 99.75%, and 99.30%, and low error rates of 0.343%, 0.358%, and 0.721% for three different types of PCB designs considered. Additionally, the model excels in precisely identifying the location of defects in the PCB images without using bounding boxes, in accordance with the description of the co-images through a segmentation approach. Overall, the proposed system effectively corrects skew, accurately detects abnormalities and outperforms traditional assessment systems.