Block Random Access Memory Research Articles

An FPGA-Implemented Antinoise Fuzzy Recurrent Neural Network for Motion Planning of Redundant Robot Manipulators.

When a robot completes end-effector tasks, internal error noises always exist. To resist internal error noises of robots, a novel fuzzy recurrent neural network (FRNN) is proposed, designed, and implemented on field-programmable gated array (FPGA). The implementation is pipeline-based, which guarantees the order of overall operations. The data processing is based on across-clock domain, which is beneficial for computing units' acceleration. Compared with traditional gradient-based neural networks (NNs) and zeroing neural networks (ZNNs), the proposed FRNN has faster convergence rate and higher correctness. Practical experiments on a 3 degree-of-freedom (DOs) planar robot manipulator show that the proposed fuzzy RNN coprocessor needs 496 lookup table random access memories (LUTRAMs), 205.5 block random access memories (BRAMs), 41384 lookup tables (LUTs), and 16743 flip-flops (FFs) of the Xilinx XCZU9EG chip.

SEU protection design for the prototype readout electronics of MAPS-based STCF inner tracker

The Super Tau Charm Facility (STCF) is a high-luminosity electron-positron collider experiment operating at center-of-mass energy of 2–7 GeV. Its primary goal is to explore flavor physics, CP-violations, and investigate physics beyond the Standard Model. The inner tracker (ITK) is a crucial component of the STCF tracking system, which is responsible for detecting particle hits, especially those with low momentum below 100 MeV/c. Its primary objectives include providing high detection efficiency and spatial resolution for charged particle tracks. However, the electronics of ITK is susceptible to single-event upset (SEU) caused by beam-related background. To address this, this paper presents a prototype of FPGA (Field Programmable Gate Array)-based electronics that can detect and automatically repair SEU induced soft errors in its Configuration Random Access Memory (CRAM) and whose Block Random Access Memory (BRAM) has been also subjected to commonly used hardening techniques. Importantly, the prototype's corrective operations do not result in any dead time due to hot redundancy backup. In the laboratory environment, we measured the bit error rate of the data transmission to be lower than 10-12 with a confidence level of 99.99%. Through neutron beam experiments conducted at China Spallation Neutron Source (CSNS) back-n white neutron source. We demonstrated that the readout electronics can effectively restore correct functionality and promptly rectify soft errors.

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

A case study: Understanding The Nature of Memories Architectures in FPGAs to Built-up Bi-CAM

his work gives a comparison between two approaches used for improving search operation speed by using FPGA-based Binary Content Addressable Memory (BiCAM), which is a parallel type of computer memory that quickly searches for and retrieves specific data stored within the memory by assigning a unique address to each piece of data. This hardware-based technique is more efficient than traditional software-based techniques such as Linear, Binary, and hash-based. The FPGA-based BiCAM is implemented using two different approaches: using Flip-flops and Block Random Access Memory as the memory element. The performance of these implementations is evaluated through Time complexity analysis, resource utilization, and search speed. The results indicate that the Flip-flops approach is worse in terms of search speed and resource utilization compared to the other approach. With the current increasing demand for faster and more efficient search operations, this approach can play an important role in optimizing search operations.

Evaluation of SEU impact on convolutional neural networks based on BRAM and CRAM in FPGAs

This study evaluates the sensitivity of FPGA-based CNN systems and the efficacy of selective hardening approaches with laser injection and proton irradiation. The LeNet-5 CNN architecture was taken as a case study. First, the entire CNN with block random access memory (BRAM) attached is evaluated by laser test scanning, and errors generated from each layer are detected to determine the most critical layer. Second, the same network is evaluated without BRAM, considering only the configuration RAM (CRAM) and errors generated from each layer are detected. Third, the impact of laser scan errors from BRAM and CRAM are compared, while tracing the layers in which these errors are generated. Then, proton testing is performed on the entire CNN, and errors from each layer are detected and compared to validate the laser scanning test. Experimental results from laser and proton demonstrate that CRAM errors have a larger impact on CNN layers than BRAM errors. Regarding layer criticality, the second convolutional layer (C2) appears to be the most critical one because it generates most CRAM errors. This was validated by serial and parallel designs, where both confirm similar trends. Accordingly, the partial triple modular redundancy (TMR) approach is only applied to the critical portions, leading to around 40 % reliability improvement with less than 20 % overhead.

An FPGA-Based Performance Analysis of Hardware Caching Techniques for Blockchain Key-Value Database

The speedy advancement in wireless communication technologies provides considerable development to enable smart cities with applications such as Intelligent Transport Systems (ITS) and the Internet of Medical Things (IoMT). Blockchain is an emerging technology that provides a secure and distributed data storage mechanism useful for smart city applications. The full nodes in the Blockchain contain a record of all the transactions and data blocks of the Blockchain users. As the number of full nodes is less and the number of Blockchain users is high, there is a huge load on the full nodes for accessing and verifying the data by the Blockchain users. Efficient hardware caching techniques are needed to decrease the data access delay. In this paper, we implement different caching techniques on the Field-Programmable Gate Array (FPGA) Network Interface Card (NIC) and analyze their performance for the key-value store caching in the Blockchain. We design the 2-way and 4-way caching techniques on Block Random-Access Memory (BRAM) and compare them with the conventional direct-mapped caching technique in terms of cache hits and cache misses. The improvements in the hit ratio of the 2-way set-associative cache technique with respect to the direct-mapped cache technique for 10 K, 25 K, and 50 K addresses are 0.8%, 0.77%, and 1.67%, respectively. On the other hand, for the same sets of addresses, the hit rate improvement of the 4-way set-associative cache technique with respect to the direct-mapped cache technique is 0.92%, 2.01%, and 2.4%, respectively. The improvements in hit rate for large data sets show that 2-way and 4-way set-associative cache techniques perform better than the direct-mapped cache technique for caching systems.

Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform

The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.

Analysis of the impact on soft error in AXI CDMA based on Xilinx Zynq-7000 FPGA

The paper discusses the impact of single-event effects (SEEs) induced by radiation in an advanced extensible interface (AXI) central direct memory access (CDMA) core based on 28 nm Xilinx ZYNQ-7000 FPGA. Soft errors of CDMA have been tested with an 241Am source using data transmitting between the block random-access memory (BRAM) and external memory (DDR3). Test results show that various kinds of failure emerge in CDMA in different work modes, such as polling and interrupting driven modes. The radiation-induced multi-cell upsets, up to 8-bit, have been observed and the SEEs cross-sections have been calculated. All experimental results demonstrate that CDMA is a key component leading to increasing sensitivity of resulting soft errors in the FPGA. The test methods and results can provide a reference for SEEs evaluation and protection of CDMA IP Core.

FPGA-Based Reconfigurable Convolutional Neural Network Accelerator Using Sparse and Convolutional Optimization

Nowadays, the data flow architecture is considered as a general solution for the acceleration of a deep neural network (DNN) because of its higher parallelism. However, the conventional DNN accelerator offers only a restricted flexibility for diverse network models. In order to overcome this, a reconfigurable convolutional neural network (RCNN) accelerator, i.e., one of the DNN, is required to be developed over the field-programmable gate array (FPGA) platform. In this paper, the sparse optimization of weight (SOW) and convolutional optimization (CO) are proposed to improve the performances of the RCNN accelerator. The combination of SOW and CO is used to optimize the feature map and weight sizes of the RCNN accelerator; therefore, the hardware resources consumed by this RCNN are minimized in FPGA. The performances of RCNN-SOW-CO are analyzed by means of feature map size, weight size, sparseness of the input feature map (IFM), weight parameter proportion, block random access memory (BRAM), digital signal processing (DSP) elements, look-up tables (LUTs), slices, delay, power, and accuracy. An existing architectures OIDSCNN, LP-CNN, and DPR-NN are used to justify efficiency of the RCNN-SOW-CO. The LUT of RCNN-SOW-CO with Alexnet designed in the Zynq-7020 is 5150, which is less than the OIDSCNN and DPR-NN.

Implementation of HD-SPWM Generation for Voltage Source Inverter Applications

The digital implementation of High-Definition Sinusoidal Pulse Width Modulation (HD-SPWM) achieves a higher accuracy and simplifies hardware design. To generate the digital PWM signal a single BRAM(Block Random Access Memory) is used. The memory allocation of the targeted FPGA device is reduced up to 43%. This reduces the number of slices (logic blocks) and LUTs, used for the implementation of HD-SPWM. The switching and sampling frequency for the generation of HD-SPWM are 20 kHz and 4 MHz respectively. The code is written in Verilog HDL and simulated in Modelsim and synthesized in Xilinx ISE. The Switching frequency achieved is 20 kHz respectively.

Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs

Static random access memory (SRAM) based field-programmable gate array (FPGA) is currently facing challenges of high leakage power and limited capacity. Replacing SRAM in FPGA with emerging nonvolatile memory (NVM) has become an effective way to solve this issue. While enjoying the advantages of NVM in power consumption and integration, nonvolatile FPGA platform is also plagued by lifetime problem. Among all components, block random access memory (BRAM) has the severest endurance problem. The state-of-the-art wear leveling strategies for NVM-based BRAMs rely heavily on static analysis. However, the static analysis would not be accurate enough for application with multiple runtime working patterns. In this article, we propose a pattern-aware wear leveling mechanism. It can improve lifetime through adaptive reconfiguration without static analysis. Evaluation shows that our mechanism can achieve 120% higher lifetime improvement with 4% performance overhead than existing performance-aware wear leveling strategy (Huai et al., 2019).

On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication

Synchronized padder block and a compact-dynamic round constant (RC) generator to achieve highly efficient Keccak architecture are proposed in this work. The proposed design yields high security with an option of 1024 bits as capacity “ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$c$ </tex-math></inline-formula> ,” while limiting the round count to less than 12 for the base design. Fusion schemes are adapted as a cost-effective approach in the base design to explore and arrive at the best efficient architecture for biometric access control application. The hybrid architecture designed as a pipeline structure with ≤2 stages eliminated the need for on-chip digital signal processor (DSP) and block random access memory (BRAM) slices. Though fusion schemes might lead to the increase in area, the minimized structural RC design coupled with a low cost architecture, ensures to achieve moderately low area. Among the proposed architectures, dual round function (Dual-f) design performed better in terms of throughput and operating frequency. Thus, when implemented, Dual-f achieved the highest efficiency of all with 12.85 Mb/s/slices and 15.11 Mb/s/slices on Virtex-5 and Virtex-7 devices, respectively. The miniature and high-speed features of the Dual-f Keccak design are found to be adequate for multimodal biometric authentication applications.

An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging.

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx-Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, 640×480 imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed.

An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme

This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">key generation</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signing</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">verification</i> operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">key generation</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signature generation</i> by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">signature verification</i> in FPGA with 8% lower hardware resource utilization.

Systematic realization of a fully connected deep and convolutional neural network architecture on a field programmable gate array

A detailed methodology for implementing a fully connected (FC) deep neural network (DNN) and convolutional neural network (CNN) inference system on a field programming gate array (FPGA) is presented. Minimal computational units are used for the DNN. For the CNN, systolic array (SA) architecture endowed with parallel processing potential is utilized. Algorithmic analysis determines the optimum memory requirement for the fixed point trained parameters. The size of the trained parameters and the available memory on the target FPGA device govern the choice of on-chip memory to utilize. Experimental results indicate that the choice of block over distributed memory saves ≈62% look-up-tables (LUTs) for the DNN ([784-512-512-10]), and the choice of distributed over block memory saves ≈30% block random access memory (BRAM) for the LeNet-5 CNN unit. This study provides insights for developing FPGA-based digital systems for applications requiring DNN and CNN.

A 4.32-ps precision Time-to-Digital Convertor using multisampling wave union method on a 28-nm FPGA

In this paper, a fully implemented field programmable gate array (FPGA) based time-to-digital converter (TDC) using multisampling wave union method (MSWU) is proposed to get higher measurement precision with lower resource utilization. Different from the previously published works based on wave union methods, an inverter-chain-based wave launcher is introduced to generate more low-jitter edges in the same operation range. Meanwhile, a new de-bubble solution combining with offline bin alignment and online bin sorting is applied to eliminate severe bubbles in FPGAs of advanced manufacturing technologies. The proposed TDCs are verified on a Virtex-7 (28 nm) of FPGA development board VC707. According to test results, the average measurement precision and mean resolution reach 4.32 ps and 0.82 ps, respectively with [-0.98;3.43] LSB DNL and [-6.06;34.1] LSB INL. A complete TDC channel only uses 831 D-type flip-flops (DFFs), 1305 look-up tables (LUTs) and 6 block random access memories (BRAMs) of 36k bits.

An Parallel FPGA SAT Solver Based on Multi‐Thread and Pipeline

The Boolean Satisfiability (SAT) problem is the key problem in computer theory and application. A parallel multi-thread SAT solver named pprobSAT+ on a configurable hardware is proposed. In the algorithm, multithreads are executed simultaneously to hide the circuit stagnate. In order to improve the working frequency and throughput of the SAT solver, the deep pipeline strategy is adopted. When all data stored in block random access memory of the field programmable gate array, the solver can achieve maximum performance. If partial data are stored in the external memory, the size of the problem instances the SAT solver can be greatly improved. The experimental results show that the speedup of three-thread SAT solver is approximately 2.4 times with single thread, and shows that the pprobSAT+ have achieved substantial improvement while a solution is found.

Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey

Content-addressable memory (CAM) is a massively parallel searching device that returns the address of a given search input in one clock cycle. Field-programmable gate array (FPGA)-based CAMs are becoming popular due to their applications in the latest networking systems, e.g., software-defined networks (SDNs) leading to upcoming 5G networks. Ternary CAM (TCAM) implements a routing table in a network router to classify and forward data packets where don’t care bits (X-bits) correspond to multiple addresses. FPGAs do not have a hard-core CAM, although it is a prime element in networking applications. This paper serves as a comprehensive survey on FPGA-based CAM/TCAMs implemented using block random-access memory (BRAM), lookup table RAM (LUTRAM), and flip-flops (FFs). BRAM-based TCAM suffers from the pre-processing of mapping data, requires the data to be in a specific order in some cases, and has a large SRAM/TCAM bit ratio. LUTRAM-based CAM/TCAM suffers from wide bit-wise ANDing, high routing complexity, but has a small SRAM/TCAM bit ratio of 14 compared to 16 in the case of BRAM-based TCAM. Shallow and wide RAM blocks are required to implement large-size RAM-based TCAMs (BRAM-based and LUTRAM-based TCAMs). FF-based TCAMs use FFs as their memory elements and have reduced hardware costs per TCAM bit. However, due to the routing complexity, it suffers from scalability and a large amount of power consumption. The update latency of BRAM-based TCAM and LUTRAM-based TCAM is proportional to the depth of BRAM and LUTRAM, respectively. However, FF-based CAM updates in 1 or 2 clock cycles depending on the availability of input/output pins on target FPGA.

Fast Mapping and Updating Algorithms for a Binary CAM on FPGA

Content-addressable memories (CAMs) are used in a variety of applications, such as IP filtering, data compression, and artificial neural networks due to its high-speed lookup. Fast field-programmable gate arrays (FPGAs) are nowadays used to emulate CAMs. These CAM emulations either make use of logical resources or use memory blocks on FPGAs to emulate CAMs. However, such CAM emulation suffers from slower mapping and updating mechanisms, which results in an unacceptable response in real-time applications. The slower response in update mechanism is proportionate to the CAM depth in the schemes. In this article, fast mapping and updating algorithms for a binary CAM (FMU-BiCAM) are presented, which efficiently utilizes lookup tables, slice registers, and block random access memories (RAMs) on Xilinx FPGA to emulate faster mapping and updating CAMs. The advantage of the proposed work lies in directly applying the CAM key as an address, which helps in updating contents in memory units. CAMs in the literature exhaust the entire CAM depth in remapping the CAM words along with the updating word, which leads to higher update latency. The proposed algorithms are implemented on Xilinx Virtex-6 FPGA, and the results show that the proposed method brings latency to only two clock cycles during update.

Designing and Validation of Block Random Access Memory based on Hardware Descriptive Language

Designing and Validation of Block Random Access Memory based on Hardware Descriptive Language