On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication

Abstract

Synchronized padder block and a compact-dynamic round constant (RC) generator to achieve highly efficient Keccak architecture are proposed in this work. The proposed design yields high security with an option of 1024 bits as capacity “ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$c$ </tex-math></inline-formula> ,” while limiting the round count to less than 12 for the base design. Fusion schemes are adapted as a cost-effective approach in the base design to explore and arrive at the best efficient architecture for biometric access control application. The hybrid architecture designed as a pipeline structure with ≤2 stages eliminated the need for on-chip digital signal processor (DSP) and block random access memory (BRAM) slices. Though fusion schemes might lead to the increase in area, the minimized structural RC design coupled with a low cost architecture, ensures to achieve moderately low area. Among the proposed architectures, dual round function (Dual-f) design performed better in terms of throughput and operating frequency. Thus, when implemented, Dual-f achieved the highest efficiency of all with 12.85 Mb/s/slices and 15.11 Mb/s/slices on Virtex-5 and Virtex-7 devices, respectively. The miniature and high-speed features of the Dual-f Keccak design are found to be adequate for multimodal biometric authentication applications.