Fast Mapping and Updating Algorithms for a Binary CAM on FPGA

Abstract

Content-addressable memories (CAMs) are used in a variety of applications, such as IP filtering, data compression, and artificial neural networks due to its high-speed lookup. Fast field-programmable gate arrays (FPGAs) are nowadays used to emulate CAMs. These CAM emulations either make use of logical resources or use memory blocks on FPGAs to emulate CAMs. However, such CAM emulation suffers from slower mapping and updating mechanisms, which results in an unacceptable response in real-time applications. The slower response in update mechanism is proportionate to the CAM depth in the schemes. In this article, fast mapping and updating algorithms for a binary CAM (FMU-BiCAM) are presented, which efficiently utilizes lookup tables, slice registers, and block random access memories (RAMs) on Xilinx FPGA to emulate faster mapping and updating CAMs. The advantage of the proposed work lies in directly applying the CAM key as an address, which helps in updating contents in memory units. CAMs in the literature exhaust the entire CAM depth in remapping the CAM words along with the updating word, which leads to higher update latency. The proposed algorithms are implemented on Xilinx Virtex-6 FPGA, and the results show that the proposed method brings latency to only two clock cycles during update.