Large-capacity high-throughput low-cost pipelined CAM using pipelined CTAM

Abstract

A novel approach toward realizing a large capacity high-throughput pipelined content addressable memory (CAM) or associative memory (AM) at low cost has been described. It employs only commercial random access memory (RAM) along with a simple binary search pipeline (BSPL). In order to search a (2/sup n/-1)-word search key field (SKF) storage RAM, the BSPL employs n identical and simple binary search processing elements, each having its local copy of the SKF storage RAM (SKFSR). The SKFSR stores, in an ordered manner, the SKFs of all the words in the CAM, whereas a data field storage RAM (DFSR) stores the unordered CAM data words. The n-times replicated SKFSR, along with the n-processor BSPL, functions as a simple n-stage pipelined content-to-address memory (CTAM). The CTAM, a new kind of memory that performs the inverse function of a RAM, serves as the first and the most important stage in the proposed 3-stage pipelined CAM architecture. In response to the stream of input query words (search keys) fed to the pipelined CAM, the pipelined CTAM first produces the corresponding stream of SKFSR addresses where the query words reside. These SKFSR addresses corresponding to the queries are next mapped back by the second stage, namely, the address mapping RAM, to their original addresses in the CAM, i.e., in the DFSR, which had been altered due to data ordering in the SKFSR. Now, the third stage of the pipelined CAM, namely, the DFSR, is read out at the mapped, i.e., the original CAM addresses, to obtain the desired stream of responses from the CAM. An augmented version of the pipelined CTAM has been designed to handle the presence of duplicate search keys in the CAM. A few illustrative examples of querying a simple database stored in the CAM have been included. The proposed pipelined CAM has a modular and highly scalable architecture. Its throughput rate, which is independent of the CAM size, is a little less than the RAM access rate and its latency is a little more than (n+2) times the RAM access time.