Block Random Access Memory Research Articles

Mitigating single event upset of FPGA for the onboard bus control of satellite

This paper proposes a hybrid anti-radiation method to enhance the reliability of Field Programmable Gate Array (FPGA), which is being applied more and more in the commercial satellite. The method utilizes the advantages of Error Detection And Correction (EDAC) and Triple Modular Redundancy (TMR). Different bus control units are improved by different anti-radiation techniques. For finite state machine, dual-port Block Random Access Memory and EDAC are utilized. EDAC is also used to enhance First In First Output unit. For the simple control register, TMR is applied to improve its anti-radiation. This hybrid method can avoid the accumulated error of TMR and reduce the complexity of system. Experimental results show that the proposed method can correct 1-bit error and detect 2-bit error effectively.

The Constant Multiplier FFT

In this paper, we present a new fast Fourier transform (FFT) hardware architecture called constant multiplier (CM) FFT. Whereas rotators in previous architectures must rotate among several different angles, the CM FFT exploits the use of constant multipliers to calculate the rotations. The paper explores the 4-parallel and 8-parallel radix-2 CM FFT, which calculates the FFT entirely by using constant multipliers. Later, radices 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> are presented, with emphasis in radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> and radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> as the best alternatives. Experimental results for a 1024-point radix-2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> CM FFT show that the proposed approach reduces the number of block random-access memories (BRAM) and digital signal processing (DSP) slices with respect to previous approaches, while achieving the highest clock frequency for a 4-parallel FFT architecture on field-programmable gate arrays (FPGAs) reported so far.

Pearl: Performance-Aware Wear Leveling for Nonvolatile FPGAs

Since static random access memory (SRAM)-based field-programmable gate array (FPGA) has limited density and comparatively high leakage power, researchers have proposed FPGA architectures based on emerging nonvolatile memories (NVMs) to satisfy the requirements of data-intensive and low-power applications. Among all components, block random access memory (BRAM) has the severest endurance problem in FPGA. Unluckily, traditional wear leveling (TWL) strategies cannot be directly applied to nonvolatile FPGA because it may induce large performance overhead. In this article, we propose performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies pertaining to coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl) are developed to balance inter-BRAM and intra-BRAM writes. Procedures, including static analysis, wear leveling-guided placement, and reconfiguration are discussed. A supportive circuit design is proposed, too. The evaluation shows that C-Pearl and F-Pearl can achieve 34% and 46% higher lifetime improvement and simultaneously 8% and 11% lower performance overhead than TWL.

RETRACTED: Reconfigurable parallelized TCAM architecture based on enhanced static memory cell

Abstract Associative memories with tristate-based web crawlers assume a vital job in systems administration switches. The hunt space requests of ternary associative memories applications are always rising. In any case, existing acknowledge where content addressable memories can enter door clusters gate arrays experience the ill effects of capacity wastefulness. The proposed idea introduces high speed search engines empowered and intertwined with many internal ports of static memory cell put together ternary associative memories structure comparing with FPGA, to accomplish an effective usage of static arrangement of memories. Previous versions of static memory cell's exploits answers for this renewable solution and also diminish maximizing expansion provided in this customary Ternary content addressable memory design specifications leading with rapid and enormous development of static memories on behalf of unique utilizing fell square Static memories called block random access memories (BRAMs) over the boards of FPGA. Nonetheless, best in class FPGAs which entitled as block RAM have a base profundity restriction, which confines the capacity productivity for ternary associative memories bits. Our proposed arrangement maintains a strategic distance from this restriction with a provision of uniting and linking the customary idea of ternary memories and its table split-ups as an alternative of partitioned squares which is so called arranged block RAMs, along these lines accomplishing associative and productive ternary CAM memory structure. The arrangement works as arrangement of basic double block memories which was planned as static memories of many input and output ports which utilizing higher parallelism, influencing speeder and vital inner clock recurrence for getting partial-squares leading to block random memories in unique individual framework cycle. Actualized this novel structure on a Virtuoso environment of version six field programmable gate array gadget. Contrasted and in the earlier versions of gate array ternary content memories plans, this strategy accomplishes speeding of two and half of its occasions faster execution of its memory unit cycle.

FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines

Boltzmann machines (BMs) are useful in various applications but are limited by their requirement to generate random numbers. In contrast, chaotic Boltzmann machines (CBMs) are neural networks that imitate the stochastic behavior of BMs with the chaotic dynamics and deterministic behavior, without random numbers. CBMs can potentially require fewer hardware resources than the original algorithms due to the unnecessity of random number generators. In this study, hardware-oriented algorithms and a differential multiply-accumulation operation are proposed to overcome the difficulties of implementing CBMs on field-programmable gate arrays (FPGAs). A hardware-oriented algorithm for CBMs, which includes fixed-point operations and shift operations, is proposed to reduce hardware resource utilization in the implemented circuits. In particular, the differential multiply-accumulate operation allows us to implement the multiply-accumulate operation with block random access memory and digital signal processors to reduce the consumption of lookup tables and flip-flops in FPGAs without losing the calculation speed. Our proposed approach was evaluated in numerical simulations, logical synthesis, and FPGA implementation. The calculation speed of FPGA-implemented CBMs was compared with software-implemented CBMs, which resulted in 1 / 6,500 of calculation time reduction in a 300-neuron CBM. Moreover, 2,048 neurons of CBM were realized by the logical synthesis. Therefore, the proposed hardware implementation of CBMs was shown to be feasible. The proposed CBMs can solve combinatorial optimization problems at a larger scale with fewer resources.

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques.

Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot$ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, no SEU errors were observed from DFF in the hardened FPGA design.

FPGA-Based Hybrid-Type Implementation of Quantized Neural Networks for Remote Sensing Applications

Recently, extensive convolutional neural network (CNN)-based methods have been used in remote sensing applications, such as object detection and classification, and have achieved significant improvements in performance. Furthermore, there are a lot of hardware implementation demands for remote sensing real-time processing applications. However, the operation and storage processes in floating-point models hinder the deployment of networks in hardware implements with limited resource and power budgets, such as field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). To solve this problem, this paper focuses on optimizing the hardware design of CNN with low bit-width integers by quantization. First, a symmetric quantization scheme-based hybrid-type inference method was proposed, which uses the low bit-width integer to replace floating-point precision. Then, a training approach for the quantized network is introduced to reduce accuracy degradation. Finally, a processing engine (PE) with a low bit-width is proposed to optimize the hardware design of FPGA for remote sensing image classification. Besides, a fused-layer PE is also presented for state-of-the-art CNNs equipped with Batch-Normalization and LeakyRelu. The experiments performed on the Moving and Stationary Target Acquisition and Recognition (MSTAR) dataset using a graphics processing unit (GPU) demonstrate that the accuracy of 8-bit quantized model drops by about 1%, which is an acceptable accuracy loss. The accuracy result tested on FPGA is consistent with that of GPU. As for the resource consumptions of FPGA, the Look Up Table (LUT), Flip-flop (FF), Digital Signal Processor (DSP), and Block Random Access Memory (BRAM) are reduced by 46.21%, 43.84%, 45%, and 51%, respectively, compared with that of floating-point implementation.

Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform

ABSTRACTOtsu’s global automatic image thresholding operation is used in various image processing applications. It needs computation of normalized cumulative histogram, mean and cumulative moments that are compute-intensive operations. In this paper, a custom architecture is presented for an efficient computation of Otsu’s algorithm along with its utilization as an intellectual property (IP) core in a field programmable gate array (FPGA) based system-on-chip (SoC) environment for the application of connected component analysis (CCA). A self-normalization technique is employed, where single-cycle, read–modify–write operations are performed with block random access memories (BRAMs) and digital signal processing (DSP)slices. The architecture is designed for 640 × 480 size of images that are captured by a high-resolution analouge camera and buffered in a DDR2 SDRAM of Xilinx ML-507 platform at 25.175 MHz clock frequency. The embedded PowerPC processor core is used to control the frame acquisition process. Experimental results on Virtex-5 xc5vfx70t FPGA device show that the architecture utilizes 1.4% slices, 2.7% BRAMs and 3.9% DSP48E slices. The total power consumption of the design is 1440.59 mW. The proposed architecture as an IP core is able to work in real-time with standard VGA resolution video and requires low computational resources.

Low‐complexity and differential power analysis (DPA)‐resistant two‐folded power‐aware Rivest–Shamir–Adleman (RSA) security schema implementation for IoT‐connected devices

The hardware security issues are emerging in crypto-algorithms of embedded portable Internet-of-Things-Devices (IoTD). The communication protocols/standards including MQTT (Message Queuing Telemetry Transport) are enforcing additional cares in device-to-system design perspectives. Due to computation-capacity limitations (CCLs) in battery-operated IoTD, heavy-duty crypto-algorithms are prohibited. This results in compromised hardware using lightweight algorithms. In this study, a new implementation schema for hierarchically-connected IoTD for indoor applications is proposed. This schema allows the IoT network to utilise strong-crypto-algorithms (i.e. RSA) instead of lightweight algorithms (i.e. attribute-based encryption (ABE)). Therefore, without increasing the consumption power or complexity, the security in the IoT network increases. This method brings about a new low CCL RSA with two-folded power-aware implementation. Furthermore, without complexity overhead, the proposed method is more secure than the conventional implementation due to the inherent countermeasure against the side-channel attacks. The presented schema is implemented on a target IoT network, utilising in XC7A100T-FPGA as IoT nodes. Furthermore, both the conventional and the proposed RSA-2048 have been implemented in Spartan6-LX75 on a SAKURA-GW board. The results show that the proposed method has reduced the RSA execution time and consumption power of IoTD at about 50 and 60%, respectively. The most noticeable drawback of the current implementation is an overhead in the range of 30-53% on block-random access memory (RAM) usage.

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.

A reconfigurable cryogenic platform for the classical control of quantum processors.

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the heart of the control infrastructure implementing the digital error-correction control loop. The platform is implemented on a field-programmable gate array (FPGA) that supports the functionality required by several qubit technologies and that can operate close to the physical qubits over a temperature range from 4 K to 300 K. This work focuses on the extensive characterization of the electronic platform over this temperature range. All major FPGA building blocks (such as look-up tables (LUTs), carry chains (CARRY4), mixed-mode clock manager (MMCM), phase-locked loop (PLL), block random access memory, and IDELAY2 (programmable delay element)) operate correctly and the logic speed is very stable. The logic speed of LUTs and CARRY4 changes less then 5%, whereas the jitter of MMCM and PLL clock managers is reduced by 20%. The stability is finally demonstrated by operating an integrated 1.2 GSa/s analog-to-digital converter (ADC) with a relatively stable performance over temperature. The ADCs effective number of bits drops from 6 to 4.5 bits when operating at 15 K.

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

This paper presents a technique to improve the reliability and the mean time to failure (MTTF) of hardware task graphs (TGs) running on reconfigurable computers. This technique, which has been named task early fetch , can be applied to a sequence of one or several applications, represented as TGs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous TG, plus increasing the redundancy level of the early fetched tasks. Experimental results on actual TGs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant TGs, and the improvement is more significant when applying to fault-tolerant TGs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at runtime and steers the execution of the running TGs. It demonstrates that, with 0.03% consumption of flip-flops and look-up tables and also 1.22% occupancy of block random access memory available on the Xilinx Virtex Ultra- Scale XCVU095-2FFVA2104E field programmable gate array, the required runtime computations can be carried out in negligible delays.

MicroBlaze implementation of GPS/INS integrated system on Virtex-6 FPGA

The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described in this paper. The inertial navigation solution and Kalman filter computations are provided by the MicroBlaze on Virtex-6 FPGA. The real time processed navigation solutions are updated with a rate of 100 Hz.

Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

Performance Analysis of Micro blaze Implemented GPS-INS Integrated Systems on Spartan 6 and Zynq FPGAs

This paper compares the performances of two loosely coupled Micro blaze Implemented GPS-INS Integrated Systems On Spartan 6 And Zynq FPGAs. The first system usesa Micro blaze implemented GPS-INS integrated system on Spartan 6 Field Programmable Gate Array (FPGA) for inertial navigation solution and Kalman filter computation.The second system uses a Micro blaze implemented GPS-INS integrated system on Zynq FPGA for inertial navigation solution and Kalman filter computation . Real time issues related to accuracy of position, GPS outages, Selective availability of GPS, Higher variances of accelerometers, Resource usage of FPGA in terms of Slices, DSP48 and Block Random Access Memory (BRAM), Computation time, latency, and power consumption are presented.The systems are designed to give real time processed navigation solutions with an update rate of 100 Hz.

Design of a high performance memory using a novel architecture of double bit CAM and SRAM

A high-speed low-power novel architecture of Dual Bit Content Addressable Memory (DB-CAM) is reported in this article. A low leakage, low power and high-speed memory has been developed using the novel architecture of DB-CAM that can store 2 bits in a single CAM block and Static Random Access Memory (SRAM). Data search operation is done by using CAM cells and SRAMs are used as data storage cells. The output of SRAM cells depend on the search result of CAM cells. To make the search operation more precise a priority detector circuit has been proposed. The new architecture of DB-CAM block reduces the power consumption, transistor count and the area on chip enormously. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre (CADENCE) using standard 90 nm CMOS technology.

AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization

In the present paper we present an architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware. Rijndael algorithm is the new AES adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES). Compared to software implementation, hardware implementation of Rijndael algorithm provides more physical security as well as higher speed. The first factor to be considered on implementing AES is the application. High-speed designs are not always desired solutions. In some applications, such as mobile computing and wireless communications, smaller throughput is demanded. Architecture presented uses memory modules (i.e., Dual-Port RAMs) of Field-Programmable Gate Array (FPGAs) for storing all the results of the fixed operations (i.e., Look-Up Table), and Digital Clock Manager (DCM) that we used effectively to optimize the execution time, reduce design area and facilitates implementation in FPGA. The architecture consumes only 326 slices plus 3 Block Random Access Memory (BRAMs). The throughput obtained was of 270 Mbits/s. The target hardware used in this paper is Spartan XC3S500E FPGA from Xilinx. Results are presented and compared with other reference implementations, as known from the technical literature. The presented architecture can be used in a wide range of embedded applications.

An Efficient Intensity Correction Algorithm for High Definition Video Surveillance Applications

The video surveillance market is increasingly moving toward cheaper, efficient, portable, and high resolution systems. A typical video surveillance system consists of several cameras, which issue warnings or initiate smart reactions according to the analysis results of the captured video data. Many algorithms in video surveillance systems assume fixed lighting conditions for the monitored area. The performance of these algorithms is severely affected by the illumination changes of the monitored area. This paper presents an efficient intensity correction algorithm for high definition video surveillance applications. The new algorithm corrects both the global and the local intensity changes. It uses an apparent gain factor to correct the global intensity changes. In addition it corrects the local intensity changes using the local intensity mean and standard deviation. The proposed algorithm shows a promising performance when compared with other intensity correction algorithms. It has a low computational cost that makes it a suitable choice for real-time hardware implementation. This paper also presents a hardware implementation of the proposed algorithm using Xilinx Spartan3A digital signal processor (DSP) XC3SD3400A device. The targeted resolution is 1920 × 1080 at 30 f/s. The hardware prototype utilizes 17% of the slices, 21% of the block random access memories, and 24% of the DSP48As available in Spartan3A DSP XC3SD3400A device.