Bit-line Technique Research Articles

A novel PVT‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub‐threshold region

AbstractThis paper presents a process voltage temperature (PVT)‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt‐trigger action in all operating modes for performance improvement, a characteristic that is not exhibited by existing SRAM cells. The action improves the stability of stored data in read and hold modes and assists the write process to enable a faster and low‐voltage write operation. Additionally, the cell uses negative bitline technique and fully‐gated grounded scheme for achieving further improvement in write ability and ION/IOFF ratio. The proposed cell shows 34.9% reduced deviation in switching threshold voltage in comparison to conventional structure. Further, improvement of up to 211% in write ability and 169% in ION/IOFF ratio is obtained over existing SRAM cells operating in sub‐threshold region. The cell takes up to 86% and 99% lesser read and write access time, respectively. The Monte‐Carlo simulations show the robust performance of proposed cell. The cell has reduced write, read, and hold failure probabilities resulting in overall Vmin of 425 mV, which is the least among the cells considered for comparison, thus making it an amenable design suitable for sub‐threshold operation under PVT‐variations.

Single Bit-Line Differential Sensing Based Real-Time NVSRAM for Low Power Applications

In this brief, we present a novel single bit-line differential programming scheme for 4T-2R NVSRAM. The NVSRAM presented in this brief not only uses an unconventional scheme of using differential sensing using a single bit-line, without the use of access transistors, but also leads an alternative transistor sizing approach for sizing the access and pull down transistors to improve write margins. The NVSRAM design used in this brief constitutes of two 3nm thick HfOx based OxRAM devices and four transistors designed at 90 nm CMOS technology node. The cell design is implemented for real-time non-volatility rather than last-bit non-volatility. Detailed analysis of the proposed single bit-line technique with parallel RRAM device programming scheme is presented in comparison to the previous NVSRAM programming schemes used for similar 4T-2R NVSRAM bit-cells.

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm

This paper presents a comprehensive overview of leakage reduction techniques prevailing in Static Random Access Memories (SRAMs) by classifying them in three categories namely latch, bitline and read port. The performance of the techniques are evaluated in terms of leakage reduction capability along with the impact on read performance and hold stability through extensive simulative investigations at 32 nm technology node by taking conventional SRAM cell as reference. Further, as SRAMs are susceptible to inter-die as well as intra-die process variations, the performance at different PVT corners is also captured to demonstrate the efficacy of each technique under PVT variations. It is found that among the techniques used for reducing latch leakages, Multi-threshold CMOS technique possess the highest leakage reduction capabilities followed by Drowsy mode and Substrate-bias techniques. The results also indicate that Negative word line technique is more effective at low supply voltages whereas the Leakage biased bitline technique is more effective at high supply voltages for reducing bitline leakages. Amongst the read port leakage reduction techniques, Stack-effect and Dynamic control of power supply rail techniques are capable of suppressing the leakages at high voltages whereas Virtual cell ground technique is more efficacious at low voltages. The impact of technology scaling on SRAM cell performance with leakage reduction techniques is also studied. For the sake of completeness, suggestions are put forward for adopting a particular technique to address leakages at latch, bitline and read port levels.

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line (BNBL) provides 47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line (NBL) and boosted bit line (BBL) write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.

Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique

In this brief, a new write assist technique is proposed to improve the write characteristics of 1T-1 magnetic tunnel junction (MTJ) spin-torque transfer memory bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write 1 operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65-nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared with the boosted wordline (BWL) technique. In addition, the proposed write assist technique leads to 12% and 48% bitcell area reduction compared with BWL and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with BWL and balanced write techniques, respectively.

Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files

Wide fan-in dynamic multiplexers are one of the critical circuits of read-out paths in high-speed register files. However, these dynamic gates have poor noise immunity, which is aggravated by their wide fan-in structure, and their high switching activity consumes significant power. We present new footer voltage feedforward domino (FVFD) and static-switching pulse domino (SSPD) designs for dynamic multiplexers. Both improve noise tolerance, and both reduce the switching power by limiting the voltage swing on the large bitline capacitance through the introduction of dual dynamic nodes. The FVFD technique is based on charge sharing, while SSPD employs a conditional pulse generator to achieve a limited-switching behavior. Adopting these dual dynamic node techniques, we implemented 32-word × 16-bits/word (0.5-Kb) 1-read, 1-write ported register files in a 1.2-V, 65-nm low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> CMOS process. Although the SSPD and FVFD techniques respectively require 2.4 and 1.4 times more area than the established single-keeper domino technique, comparative analysis through simulations and measurement results suggests that they can be advantageous in terms of both read power and noise immunity.

Design of an 8-cell Dual Port SRAM in 0.18-&amp;#956;m CMOS Technology

Low power and low area Static Random Access Memory (SRAM) is essential for System on Chip (SoC) technology. Dual-Port (DP) SRAM greatly reduces the power consumption by full current-mode techniques for read/write operation and the area by using Single-Port (SP) cell. An 8 bit DP-SRAM is proposed in this study. Negative bit-line technique during write has been utilized for write-assist solutions. Negative voltage is generated on-chip using capacitive coupling. The proposed circuit design topology does not affect the read operation for bit interleaved architectures enabling high-speed operation. Designed in 0.18-μm CMOS process, the area is only 1.2 times of the SP-SRAM and its power is 1.3 times of the SP-SRAM when the two ports simultaneously work at the same frequency. Simulation results and comparative study of the present scheme with state of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption. The proposed negative bit- line technique can be used to improve the write ability of 6 T Single-Port (SP) as well as 8 T DP and other multiport SRAM cells.

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme

This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - Vtn and therefore saves the active power in the half-selected columns (where Vtn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125°C. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the Vtn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-µW/MHz writing energy and 72.8-µW leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 µW/MHz (12.9 pJ/access) at a supply voltage of 0.5V and operating frequency of 6.25MHz in a 50%-read/50%-write operation.

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

The increased device variations, lower supply voltages have enforced the usage of write-assist circuits in static random access memory (SRAMs) in the nano-complementary metal oxide semiconductor (CMOS) regime. Negative bit-line scheme during write has been found one of the most promising write-assist solutions. A new low power, negative bit-line scheme is presented. The presented negative bit-line technique can be used to improve the write ability of 6 T single-port (SP) as well as 8 T dual-port (DP) and other multiport SRAM cells. Negative voltage is generated on-chip using capacitive coupling. Only the bit-line on which a '0' is to be written is taken negative during write operation. The proposed circuit design topology does not affect the read operation for bit-interleaved architectures enabling high-speed operation. Simulation results and comparative study of the present scheme with state-of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption.

Twisted bit-line technique for multi-gigabit DRAMs

A new twisted bit-line (TBL) technique is presented to reduce bit-line coupling noise for multi-gigabit DRAMs. Sufficient noise reduction effects have been monitored through soft-error rate measurement on test chips using the proposed TBL technique. Also, the problem of excessive chip area penalty in the conventional TBL techniques can be solved in the proposed TBL technique.