Twisted bit-line technique for multi-gigabit DRAMs

Abstract

A new twisted bit-line (TBL) technique is presented to reduce bit-line coupling noise for multi-gigabit DRAMs. Sufficient noise reduction effects have been monitored through soft-error rate measurement on test chips using the proposed TBL technique. Also, the problem of excessive chip area penalty in the conventional TBL techniques can be solved in the proposed TBL technique.