Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs

Dong-Sun Min Dong-Sun Min,D.W Langer

doi:10.1109/cicc.1999.777280

Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs

Dong-Sun Min Dong-Sun Min, D.W Langer

https://doi.org/10.1109/cicc.1999.777280

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Publication Date: May 16, 1999

Citations: 3

Affiliation: Motorola (United States), University of Pittsburgh

#Word Line #Coupling Noise Reduction + Show 8 more

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Abstract

New multiple twisted data line techniques to reduce both bit line (BL) and word line (WL) coupling noises in scaled embedded DRAMs are proposed and analyzed. An improved noise/signal ratio resulting from the application of the proposed techniques is confirmed by soft-error rate measurements on test chips with 256-Mbit and 1-Gbit level integration. At the 256-Mbit level, when the proposed techniques are applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional twisted Bl (TBL) and WL schemes.

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