Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files

Abstract

Wide fan-in dynamic multiplexers are one of the critical circuits of read-out paths in high-speed register files. However, these dynamic gates have poor noise immunity, which is aggravated by their wide fan-in structure, and their high switching activity consumes significant power. We present new footer voltage feedforward domino (FVFD) and static-switching pulse domino (SSPD) designs for dynamic multiplexers. Both improve noise tolerance, and both reduce the switching power by limiting the voltage swing on the large bitline capacitance through the introduction of dual dynamic nodes. The FVFD technique is based on charge sharing, while SSPD employs a conditional pulse generator to achieve a limited-switching behavior. Adopting these dual dynamic node techniques, we implemented 32-word × 16-bits/word (0.5-Kb) 1-read, 1-write ported register files in a 1.2-V, 65-nm low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> CMOS process. Although the SSPD and FVFD techniques respectively require 2.4 and 1.4 times more area than the established single-keeper domino technique, comparative analysis through simulations and measurement results suggests that they can be advantageous in terms of both read power and noise immunity.