Highly robust Finfet based wide Fan-in dynamic OR gate with dynamic threshold voltage control

Abstract

Wide Fan-in dynamic OR gate has always been an integral part of high speed microprocessors. But dynamic logic gate suffers from low noise immunity. A weak PMOS keeper was introduced to increase the noise immunity. Keeper technique acts as a compensatory mechanism for charge loss due to leakage current and maintains high noise immunity while allowing leakage current through dynamic gate. A large size keeper is used for wide fan-in dynamic OR gate which allows large leakage current through the dynamic gate. This large leakage current unnecessarily results in large power dissipation which can be a critical factor for the microprocessors used in portable battery operated devices. Recently double gate Finfet has been reported to reduce leakage current effectively through it using threshold voltage control through back gate biasing technique. In this paper a new Finfet based wide fan-in dynamic OR gate has been proposed with reduced leakage and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining high noise immunity as compared to basic dynamic OR gate.