Binary Memory Cells Research Articles

Helitronics as a potential building block for classical and unconventional computing

Magnetic textures are promising candidates for unconventional computing due to their non-linear dynamics. We propose to investigate the rich variety of seemingly trivial lamellar magnetic phases, e.g. helical, spiral, stripy phase, or other one-dimensional soliton lattices. These are the natural stray field-free ground states of almost every magnet. The order parameters of these phases may be of potential interest for both classical and unconventional computing, which we refer to as helitronics. For the particular case of a chiral magnet and its helical phase, we use micromagnetic simulations to demonstrate the working principles of all-electrical (i) classical binary memory cells and (ii) memristors and artificial synapses, based on the orientation of the helical stripes.

Switchable Optically Active Schottky Barrier in La0.7Sr0.3MnO3/BaTiO3/ITO Ferroelectric Tunnel Junction

AbstractOne of the most desirable attributes of non‐volatile memories and memristors is a fast and non‐destructive read out of their resistive state. Prototypical ferroelectric (FE) memories use the bulk photovoltaic response associated to the polarization of FE films to address this requirement by optically sensing binary memory cells. A more advanced type of non‐volatile memories is FE tunnel junctions (FTJs). They feature resistive state ratios RHigh/RLow up to 106, with a continuum of resistive states accessible, making them promising candidates for neuromorphic computing applications. A novel approach is presented to achieve the optical sensing of the resistive state in a La0.7Sr0.3MnO3/BaTiO3/ITO FTJ, by using the Schottky barrier forming in the La0.7Sr0.3MnO3/BaTiO3 interface to dramatically enhance the optical response of the 5 nm BaTiO3 (BTO) barrier. Illumination with UV light exceeding the BTO bandgap through the top transparent ITO electrode generates a photovoltaic response in the RHigh state, with an open circuit voltage Voc of 400 mV at 20 K, enabling the optical sensing of the resistive state. In the RLow state, the Schottky barrier is removed and the photoresponse disappears.

Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell

A memristor-transistor hybrid ternary content addressable memory (MTCAM) with a memristor-based ternary memory cell is proposed. New emerging devices like memristors have recently been explored to overcome the limitations of CMOS-based memory circuits. The memristor is used as a binary memory cell in these MTCAM designs to replace a CMOS-based memory cell. This proposed design used a memristor as a ternary memory cell by exploiting its variable resistance characteristics. The associated wiring is reduced almost by a factor of 2 as a ternary cell is used instead of two binary cells. Area efficiency is further enhanced as the MTCAM cell is comprised of two transistors and two memristors (2T2M). A segmentation technique of match line along with a robust write/search operation method is presented to enhance the search speed of the proposed MTCAM. Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. Simulation results show the worst search delay of 0.75 ns and the energy/bit/search of 0.866 fJ for the 128 × 128 bit MTCAM.

Low storage power and high noise margin ternary memory cells in nanoelectronics

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.

Analogue pattern recognition with stochastic switching binary CMOS-integrated memristive devices

Biological neural networks outperform current computer technology in terms of power consumption and computing speed while performing associative tasks, such as pattern recognition. The analogue and massive parallel in-memory computing in biology differs strongly from conventional transistor electronics that rely on the von Neumann architecture. Therefore, novel bio-inspired computing architectures have been attracting a lot of attention in the field of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are employed to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology to neuromorphic systems. However, dealing with the inherent stochasticity of resistive switching can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail, and their potential applications in stochastic artificial neural networks (StochANNs) capable of solving MNIST pattern recognition tasks is examined. A mixed-signal implementation with hardware synapses and software neurons combined with numerical simulations shows that the proposed concept of stochastic computing is able to process analogue data with binary memory cells.

Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

This work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with the voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) characteristics associated with PWL two-terminals to be electronically adjustable via the external DC voltage. Numerical analysis of designed binary memory cell covers all mandatory parts: phase portraits, calculation of the largest Lyapunov exponent (LLE), basins of attraction for the typical strange attractors, and high-resolution circuit-oriented bifurcation sequences. A transition from the stable states toward chaotic regime through metastability is proved via real measurement. The robustness of the generated chaotic attractors is verified by captured oscilloscope screenshots.

Asymmetric pulsing for reliable operation of titanium/manganite memristors

We present a pulsing protocol that significantly increases the endurance of a titanium-manganite interface used as a binary memory cell. The core of this protocol is an algorithm that searches for the proper values for the set and reset pulses, canceling the drift in the resistance values. A set of experiments show the drift-free operation for more than 105 switching cycles, as well as the detrimental effect by changing the amplitude of pulses indicated by the protocol. We reproduced the results with a numerical model, which provides information on the dynamics of the oxygen vacancies during the switching cycles.

Novel electronic circuit element for ternary use

A ternary cell based on a novel electronic circuit element with field effect operation is presented. The new non-inverting element has unique properties with a negative resistance characteristic over its complete range. It has been designed for use in complementary multiple-valued digital systems. Ternary and binary memory cells with a feedback resistor are presented. Without this resistor the memory cells act as a driver. Binary use is also possible in mixed ternary/binary circuits within one physical technology. This mixed use is necessary for the communication with binary systems.

Complexity of decoders--I: Classes of decoding rules

Several classes of decoding rules are considered here including block decoding rules, tree decoding rules, and bounded-distance and minimum-distance decoding rules for binary parity-check codes. Under the assumption that these rules are implemented with combinational circuits and sequential machines constructed with AND gates, OR gates, INVERTERS, and binary memory cells, bounds are derived on their complexity. Complexity is measured by the number of logic elements and memory cells, and it is shown that minimum-distance and other decoders for parity-check codes can be realized with complexity proportional to the square of block length, although at the possible expense of a large decoding time. We examine tradeoffs between probability of error and complexity for the several classes of rules.