Binary Full Adder Research Articles

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.

Design and simulation of a binary full adder based on quantum rings

In this paper, a binary full adder circuit is designed with eight quantum rings where each ring is threaded by a magnetic flux which is an odd multiple of half of the magnetic flux quantum. The quantum rings are divided into two categories with four rings connected to each other in parallel. They are attached symmetrically to two semi-infinite one-dimensional metallic electrodes , and three gate voltages are applied as three inputs of the full adder. The Hamiltonian of the system is approximated by the tight-binding method, and the calculations are performed by using Green's function formalism. The current-voltage characteristics are obtained for different values of applied gate voltages in the strong and weak-coupling strengths between the quantum rings and source and drain electrodes. The results are in accordance with the truth table of a binary full adder and show this quantum circuit behaves as a binary full adder. • This work proposes a binary full adder consisting of eight quantum rings where a constant magnetic flux is passing through each of them. • The designed full adder with eight quantum rings is divided into two separate parts (Sum and Carry-out) which are connected symmetrically to the source and drain electrodes. • The values of the applied gate voltages are considered as the full adder inputs and the electric current is the output of the system. • The output current of the proposed circuit based on the system input voltages is in accordance with the truth table of a binary full adder.

Efficient Parallel Multi‐Bit Logic‐in‐Memory Based on a Ultrafast Ferroelectric Tunnel Junction Memristor

AbstractMemristive logic‐in‐memory (LIM) is an attractive candidate for in‐memory computing and thus would overcome some of the issues concerning the von Neumann bottleneck, which has been intensively investigated. Here, a multi‐bit and functionally complete LIM strategy is designed to efficiently perform multi logical functions in parallel. This strategy is experimentally demonstrated by a multi‐bit ferroelectric tunnel junction (FTJ) memristor with a sub‐nanosecond operation speed which is nearly two orders of magnitude faster than the previous memristive LIM. Using the four resistance states (2‐bit) of only a single FTJ memristor cell, two logical computations are successfully performed in parallel, and the 16 complete Boolean logic functions are implemented within only two steps. In addition, the multi‐encoding schemes are proposed to further improve the efficiency and flexibility of parallel logical computations. Accordingly, the 1‐bit binary full adder can be implemented using as less as three parallel memristors by only performing five steps, and on this basis the N‐bit full adder can also be realized. These results provide a highly efficient LIM approach, which could be a promising candidate for future computing architecture.

Improved Design of Binary Full Adder

Improved Design of Binary Full Adder

Ternary inverter gate designs using OPV5-based single-molecule field-effect transistors

Over recent decades, much effort has been invested in the implementation of digital circuits using multivalued and fuzzy logic, as they are more similar to real-world arithmetic and logic. Ternary logic can be implemented in molecular electronics using transistors based on benzene rings because of their special characteristics. A dual-gate molecular field-effect transistor based on the oligo (phenylene vinylene) molecule, which consists of aromatic rings, is proposed herein. Moreover, models for the implementation of all the different types of ternary inverter, viz. a negative ternary inverter, standard ternary inverter, and positive ternary inverter, as well as a binary full adder (FA) cell are proposed. Of note, each of the ternary inverters is implemented using just one transistor, while the FA cell is implemented using two transistors. The transistor, the inverters, and the FA cell are simulated using standard tools to verify their functionality.

Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate

In this letter, we introduce the magnetic quantum-dot cellular automata (MQCA) based area and speed efficient design approach for nanomagnetic full adder implementation. We exploited the physical properties of three input MQCA majority gate (MG), where the fixed input of the MG is coupled ferromagnetically to one of the primary input operands. Subsequently we propose a design methodology, mapping logic and micromagnetic software implementation, validation of the binary full adder architecture built using two–three inputs MQCA MGs. In addition, we also analyzed our proposed design for switching errors to ensure bit stability and reliability. Our proposed design leads to ∼36%–69% reduction in the number of nanomagnets, ∼50%–75% reduction in the number of clock cycles and ∼33%–50% reduction in the number of MG operations required for the binary full adder implementation compared to the state of art designs.

Memristor‐Based Efficient In‐Memory Logic for Cryptologic and Arithmetic Applications

AbstractAs the era of big data dawns, conventional digital computers face increasing difficulties in performance and power efficiency due to their von Neumann architecture, leading to an urgent requirement for computing paradigms that can merge logic and memory. An efficient in‐memory logic approach based on unipolar memristors that is capable of implementing all 16 Boolean logic functions in the same cell in less than 3 logic steps using a thermochemical metallization cell, where the confinement of filament diameter and thus switching location have reduced the threshold voltages and improved the switching uniformity, is experimentally demonstrated. The high efficiency of the logic units allows for the construction of novel encryption hardware in which both the encryption and decryption processes are achieved by memristor logic while the encryption key is also generated from the intrinsic stochasticity of resistive switching. The memristive array is also used to implement the calculation of Hamming distance and 1‐bit binary full adder with high efficiency, thus paving a way for future non‐von Neumann computing architectures.

Shape and Positional Anisotropy Based Area Efficient Magnetic Quantum-Dot Cellular Automata Design Methodology for Full Adder Implementation

Magnetic quantum-dot cellular automata (MQCA) based computation started emerging as the Moore's law approaching towards its end. Number of nanomagnets and the area occupancy are major constraints in materializing this MQCA-based digital arithmetic circuit design. In this letter, we propose a design methodology and demonstrate the hybrid approach of using slant edged input and 45 $^\circ$ aligned nanomagnets for optimized binary full adder design. Asymmetric shape anisotropy nanomagnets pave the way for standalone inputs, whereas positional anisotropy reduces the signal loss in transmission of data and enables lossless information propagation. This complementary property of both shape and positional anisotropy leads to exploiting the energy minimization nature of nanomagnets, reducing the design footprint. Further, to enable the multipurpose scaling, horizontal and vertical layouts of the nanomagnetic computing design of full adder has been proposed. Our proposed nanomagnetic adder architecture leads to 28% reduction in the total number of nanomagnets compared to the state of the art design, leading to an area efficient architectural design.

Optimized design and performance analysis of novel comparator and full adder in nanoscale

AbstractIn a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are es...

Binary full adder, made of fusion gates, in a subexcitable Belousov-Zhabotinsky system.

In an excitable thin-layer Belousov-Zhabotinsky (BZ) medium a localized perturbation leads to the formation of omnidirectional target or spiral waves of excitation. A subexcitable BZ medium responds to asymmetric local perturbation by producing traveling localized excitation wave-fragments, distant relatives of dissipative solitons. The size and life span of an excitation wave-fragment depend on the illumination level of the medium. Under the right conditions the wave-fragments conserve their shape and velocity vectors for extended time periods. I interpret the wave-fragments as values of Boolean variables. When two or more wave-fragments collide they annihilate or merge into a new wave-fragment. States of the logic variables, represented by the wave-fragments, are changed in the result of the collision between the wave-fragments. Thus, a logical gate is implemented. Several theoretical designs and experimental laboratory implementations of Boolean logic gates have been proposed in the past but little has been done cascading the gates into binary arithmetical circuits. I propose a unique design of a binary one-bit full adder based on a fusion gate. A fusion gate is a two-input three-output logical device which calculates the conjunction of the input variables and the conjunction of one input variable with the negation of another input variable. The gate is made of three channels: two channels cross each other at an angle, a third channel starts at the junction. The channels contain a BZ medium. When two excitation wave-fragments, traveling towards each other along input channels, collide at the junction they merge into a single wave-front traveling along the third channel. If there is just one wave-front in the input channel, the front continues its propagation undisturbed. I make a one-bit full adder by cascading two fusion gates. I show how to cascade the adder blocks into a many-bit full adder. I evaluate the feasibility of my designs by simulating the evolution of excitation in the gates and adders using the numerical integration of Oregonator equations.

All-Optical Binary Full Adder Using Logic Operations Based on the Nonlinear Properties of a Semiconductor Optical Amplifier

We propose a new and potentially integrable scheme for the realization of an all-optical binary full adder employing two XOR gates, two AND gates, and one OR gate. The XOR gate is realized using a Mach-Zehnder interferometer (MZI) based on a semiconductor optical amplifier (SOA). The AND and OR gates are based on the nonlinear properties of a semiconductor optical amplifier. The proposed scheme is driven by two input data streams and a carry bit from the previous less-significant bit order position. In our proposed design, we achieve extinction ratios for Sum and Carry output signals of 10 dB and 12 dB respectively. Successful operation of the system is demonstrated at 10 Gb/s with return-to-zero modulated signals.

Comparative Study on Energy-Efficiencies of Single-Electron Transistor-Based Binary Full Adders Including Nonideal Effects

Performances and energy efficiencies of various single-electron transistor-based (SET-based) binary full adders (FAs) are comparatively investigated with optimization of device parameters by means of simulation program with integrated circuit emphasis models including nonideal effects commonly observed in really implemented SETs. The proposed binary decision diagram (BDD) cell-based 1-bit FA is the most promising in terms of energy efficiency (τ=0.3 aJ/state), power dissipation (P = 1.2 nW), delay (τ=20 ps), and immunity to process variations (background charge noise ΔQ0 <; ±0.112q and control gate capacitance mismatch ΔCcg <; 0.5 × Ccg) at the expense of hardware burden, compared with majority gate-based SET FAs (3.988 aJ/state, P = 15.95nW, τ=52 ps, ΔQ0 <; ±0.0392q, ΔCcg <; 0.35 × Ccg) and SET threshold logic gate-based FAs (3.845 aJ/state, P=15.38nW, τ=107 ps, ΔQ0 <; ±0.028q, ΔCcg <; 0.2 × Ccg). It is also found that the SET itself dominates the power dissipation in SET-based FAs and the static dc power plays a significant role in power consumption in SET-based FAs, compared with the dynamic power, regardless of the FA type. In addition, SET-based BDD FAs are compared with their CMOS counterparts.

An all optical method of implementing a wavelength encoded simultaneous binary full adder–full subtractor unit exploiting nonlinear polarization rotation in semiconductor optical amplifier

Full adders and full subtractors are the basic circuit elements of any digital data processor in electronics as well as in the all optical domain. Again the wavelength dependent encoding/decoding techniques have established itself as a very promising and efficient tool having some inherent and unique advantages relative to the other well known intensity or polarization or phase dependent optical data encoding mechanisms. In this communication, the authors therefore propose a new scheme of implementing a wavelength encoded complete binary full adder–full subtractor unit in the all optical domain using the wavelength conversion by the nonlinear polarization rotation in a single semiconductor optical amplifier. The interacting signals are counter propagating in the semiconductor optical amplifier and hence can be set at the same wavelength. To realize the binary logic wavelength dependent encoding/decoding mechanism is exploited in our proposed scheme of full adder–full subtractor unit. Also the optical add/drop multiplexing employing the special filtering property of the semiconductor optical amplifier is utilized for the designing of the all optical system.

Optical computation based on nonlinear total reflectional optical switch at the interface

A new scheme of binary half adder and full adder is proposed. It realizes a kind of all-optical computation which is based on the polarization coding technique and the nonlinear total reflectional optical switches.

Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part II

Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part IIWe continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the Redundant Signed Digit (RSD) operations, then prove its stability of the calculations. Generally, one-bit binary full adder assumes positive weights to all of its three binary inputs and two outputs. We define the circuit structure of two-types n-bit GFAs using the recursive construction to use the RSD arithmetic logical units that we generalize full adder to have both positive and negative weights to inputs and outputs. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: GFACIRC2, version: 7.8.09 4.97.1001

Logical synthesis of moltivalued symmetric function based on binary full adders

This paper discusses the definition and properties of multivalued symmetric functions, points out that a multivalued symmetric function can be decomposed according to the value of the functionj. The subfunctionL j corresponding toj must be a symmetric function, and it may be expressed as the sum of products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the circuit realization for the multivalued symmetric functions based on full adders is proposed.

Implementation of a binary optical full adder using a Venn diagram and optical phase conjugation

Conventional optical pattern logic schemes can only process two input variables at a time. We propose a new optical spatial encoding scheme that is capable of simultaneously processing multiple input variables. Based on this new scheme an optical full adder was experimentally demonstrated using a picosecond optical phase-conjugation device.

Design of polarization-encoded optical shadow-casting logic units using truth-table partitioning

The input pixel size of a polarization-encoded optical shadow-casting logic system is reduced by means of truth-table partitioning. The proposed design algorithm is used to encode the inputs of a three-input, two-output binary full adder. A comparison with alternative designs proves that the technique leads to an improved memory-efficient optical computing unit.

Digital Optical Logic Using A Pulsed Sagnac Interferometer Switch

The use of a new Sagnac interferometer switch (SIS) to perform digital optical logic is described. The optical logic switch consists of a Sagnac interferometer with an optical nonlinear material in its loop. Both the SIS input and output logic variables are optical pulses. The output SIS state is a function of the initial mirror alignment and the state of the inducing light beam. Using various SIS interconnections, all 16 two-variable binary logic functions can be implemented. Parallel logic processing of different logic functions can be performed using a single Sagnac interferometer. Since SIS elements are cascadable, sequential operation is also possible. As an example, an implementation of the SIS optical binary full adder is illustrated. If one input is a cw analog signal and another input is an ultrafast optical pulse train, the SIS can also be used as an ultrafast optical sampling device. Conditions for proper optical sampling frequency are presented.

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this correspondence, the implementation of pipelined binary parallel counters with networks of latched quaternary threshold logic full adders is described and compared with the implementation using networks of latched binary full adders. Since each signal variable in quaternary logic may assume four logical states, twice the informational content of a binary variable, an over 50 percent savings in the total number of intermediate signal variables required to implement the parallel counter results. With the new quaternary logic circuits we will employ, over 40 percent fewer transistors and resistors are necessary for the implementation of pipelined binary parallel counters. The combination of these two factors could provide significantly reduced die areas for integrated pipelined parallel counters.