Binary Decision Diagram Node Research Articles

On Minimal Cut Sets Representation with Binary Decision Diagrams

Since their introduction in form of a canonical representation of logical functions, the Binary Decision Diagrams (BDDs) gained a wide acceptance in numerous industrial applications. This paper summarizes the properties of BDD representation of Minimal Cut Sets (MCS) of Fault Tree (FT) models most typically encountered in nuclear energetics. Cut sets from MCS are defined as paths from the top BDD node to terminal nodes in the BDD, on which a quantitative and qualitative FT analysis (FTA) is performed. The core of the FTA on the BDDs is performed with help of two fundamental algorithms, one for conditional probability evaluation and another for the selection of cut sets. The accuracy of conditional probability evaluation represents an essential feature for an unbiased quantitative analysis, such as the top event probability or the determination of event importance measures. The cut set selection algorithm is shown in a generic version introducing logical predicates for its selection criteria. As it is known, the efficiency of depicted algorithms depends only on the number of BDD nodes used for the FT representation. In order to appraise the compactness of the BDD representation of FT models, their characteristics have herein been evaluated on several real-life models from the Nuclear Power Plant Krško. The extraordinariness of the compactness of the BDD representation reflects in its ability to implement advanced dynamic analysis (i.e. what-if) of FT models. The efficiency of such an approach is recognized by commercial vendors upgrading their FT Tools to new versions by implementing BDD based algorithms.

A method for transformation from dynamic fault tree to binary decision diagram

Dynamic fault tree (DFT) is a powerful modeling approach for reliability analysis of complex system with dynamic failure behaviors. In reality, the tree structure may be highly coupled either by shared basic events or by the high-level dynamic gates. Currently, the application of sequential binary decision diagram (SBDD)-based method for quantitative analysis of such highly coupled DFTs is mainly limited to DFTs whose dynamic gates locate in the bottom of the tree. Moreover, there is no efficient way dealing with the dependencies among different nodes of a SBDD 1-path. This paper makes an improvement to the SBDD-based approach. A generation procedure is proposed to directly construct the binary decision diagram (BDD) model for a DFT with arbitrary tree structure. During the construction, the sequential-dependent information of the tree is derived as several BDD nodes, each indicates a binary-sequential event representing the sequence of two occurred basic events. A topological sorting is applied on each 1-path of the resultant BDD to obtain its contained disjoint cut sequences. Based on this, both qualitative and quantitative analysis can be performed on the DFT with no limitations on tree structure, and its minimal cut sequence set (CSS) is obtained as disjoint. Examples are provided for verification and comparison, and the results illustrate the merits of the proposed approach.

Reversible Circuit Synthesis Time Reduction Based on Subtree-Circuit Mapping

Several works have been conducted regarding the reduction of the energy consumption in electrical circuits. Reversible circuit synthesis is considered to be one of the major efforts at reducing the amount of power consumption. The field of reversible circuit synthesis uses a large number of proposed algorithms to minimize the overall cost of circuits synthesis (represented in the line number and quantum cost), with minimal concern paid for synthesis time. However, because of the iterative nature of the synthesis optimization algorithms, synthesis time cannot be neglected as a parameter which needs to be tackled, especially for large-scale circuits which need to be realized by cascades of reversible gates. Reducing the synthesis cost can be achieved by Binary Decision Diagrams (BDDs), which are considered to be a step forward in this field. Nevertheless, the mapping of each BDD node into a cascade of reversible gates during the synthesis process is time-consuming. In this work, we implement the idea of the subtree-based mapping of BDD nodes to reversible gates instead of the classical nodal-based algorithm to effectively reduce the entire reversible circuit synthesis time. Considering Depth-First Search (DFS), we convert an entire BDD subtree in one step into a cascade of reversible gates. A look-up table for all possible combinations of subtrees and their corresponding reversible gates has been constructed, in which a hash key is used to directly access subtrees during the mapping process. This table is constructed as a result of a comprehensive study of all possible BDD subtrees and considered as a reference during the conversion process. The conducted experimental tests show a significant synthesis time reduction (around 95% on average), preserving the correctness of the algorithm in generating a circuit realizing the required Boolean function.

An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)

The memristor is considered as the fourth fundamental circuit element along with resistor, capacitor and inductor. It is a two-terminal passive circuit element whose resistance value changes based on the amount of charge flowing through it. Another property of the memristor is that its resistance change is non-volatile in nature, and hence can be used for non-volatile memory applications. Researchers have been exploring memristors from various perspectives such as logic design and storage applications. In this paper, a slicing crossbar architecture for the efficient mapping of Boolean functions is proposed which exploits gate level parallelism using the memristor aided logic (MAGIC) design style. A Boolean function is first represented as a Binary Decision Diagram (BDD). The BDD nodes are expressed as netlists of NOR and NOT gates, and are mapped to the proposed slicing crossbar architecture with parallel node evaluation where possible. This is the first approach that combines BDD-based synthesis with MAGIC gate evaluation on memristor crossbar, while at the same time avoiding crossbar-related problems using a slicing architecture. Experimental evaluations on standard benchmark functions show considerable improvement in the solutions.

Efficient construction of binary decision diagrams for network reliability with imperfect vertices

This paper discusses evaluation of the network reliability with imperfect vertices, which computes the probability that a subset of nodes is communicable under possible failures of links and nodes. Although the network reliability is efficiently computed utilizing a binary decision diagram (BDD) if assuming link failures only, it can be 10 times slower if considering node failures as well. This is because existing algorithms are designed to repeatedly update a BDD for every node failure in a step-by-step manner. This research proposes an algorithm that creates the final BDD without the redundant repetitions, which greatly improves the computation efficiency. Moreover, this paper presents a better variable order of BDDs among variables corresponding to links and nodes. Under the variable order, the proposed algorithm is compared with existing ones by numerical experiments using various benchmark networks including real communication networks. The results show that the proposed algorithm runs 198.2 times faster than the existing ones for the 10-by-10 grid graph, 1074.6 times faster for the complete graph with 12 vertices, and 65.6 times faster for some well-known benchmark network. For some network instances, the proposed variable order reduces the number of BDD nodes by 15–38% compared with the existing order. This paper reveals that considering imperfect vertices does not impose significant performance overheads.

Selective MBE growth of hexagonal networks of trapezoidal and triangular GaAs nanowires on patterned (1 1 1)B substrates

As a combination of novel hardware architecture and novel system architecture for future ultrahigh-density III–V nanodevice LSIs, the authors’ group has recently proposed a hexagonal binary decision diagram (BDD) quantum circuit approach where gate-controlled path switching BDD node devices for a single or few electrons are laid out on a hexagonal nanowire network to realize a logic function. In this paper, attempts are made to establish a method to grow highly dense hexagonal nanowire networks for future BDD circuits by selective molecular beam epitaxy (MBE) on (1 1 1)B substrates. The (1 1 1)B orientation is suitable for BDD architecture because of the basic three-fold symmetry of the BDD node device. The growth experiments showed complex evolution of the cross-sectional structures, and it was explained in terms of kinetics determining facet boundaries. Straight arrays of triangular nanowires with 60 nm base width as well as hexagonal arrays of trapezoidal nanowires with a node density of 7.5×10 6 cm −2 were successfully grown with the aid of computer simulation. The result shows feasibility of growing high-density hexagonal networks of GaAs nanowires with precise control of the shape and size.

Properties of a GaAs Single Electron Path Switching Node Device Using a Single Quantum Dot for Hexagonal BDD Quantum Circuits

A new single electron (SE) binary-decision diagram (BDD) node device having a single quantum dot connected to three nanowire branches through tunnel barriers was fabricated using etched AlGaAs/GaAs nanowires and nanometer-sized Schottky wrap gates (WPGs), and their operation was characterized experimentally, for the hexagonal BDD quantum circuit. Fabricated devices showed clear and steep single electron pass switching by applying only an input voltage signal, which was completely different from switching properties in the previous SE BDD node devices composed of two single electron switches. As the possible switching mechanism, the correlation between the probabilities of tunnelling thorough a single quantum dot in exit branches was discussed.

Embedded Nanowire Network Growth and Node Device Fabrication for GaAs-Based High-Density Hexagonal Binary Decision Diagram Quantum Circuits

The basic feasibility of constructing hexagonal binary decision diagram (BDD) quantum circuits on GaAs-based selectively grown (SG) nanowires was investigated from viewpoints of electrical connections through embedded nanowires and electrical uniformity of devices formed on nanowires. For this, <110>- and <510>-oriented nanowires and hexagonal network structures combining these nanowires were formed on (001) GaAs substrates by selective molecular beam epitaxy (MBE) growth. The width and vertical position of the nanowires could be controlled by growth conditions for both <110>- and <510>-directions. By current–voltage (I–V) measurements, good electrical connection was confirmed at the node point where vertical alignment of embedded GaAs nanowire pieces was found to be important. SG quantum wire (QWR) switches formed on the nanowires showed good gate control over a wide temperature range with clear conductance quantization at low temperatures. Good device uniformities were obtained on the test chips, providing a good prospect for future integration. BDD node devices using SG QWR switches showed clear path switching characteristics. Estimated power-delay product values were very small, confirming the feasibility of ultra low-power operation of future circuits.

Fast computation of symmetries in boolean functions

Symmetry detection in completely specified Boolean functions is important for several applications in logic synthesis, technology mapping, binary decision diagram (BDD) minimization, and testing. This paper presents a new algorithm to detect four basic types of two-variable symmetries. The algorithm detects all pairs of symmetric variables in one pass over the shared BDD of the multioutput function. The worst case complexity of this method is cubic in the number of BDD nodes, but on typical logic synthesis benchmarks the complexity appears to be linear. The computation is particularly efficient when the functions have multiple symmetries or no symmetries. Experiments show that the algorithm is faster than other known methods, and in some cases achieves a speedup of several orders of magnitude.

Single-electron AND/NAND logic circuits based on a self-organized dot network

We experimentally demonstrated single-electron operations of an AND/NAND logic circuit based on a self-organized GaAs quantum-dot (QD) network fabricated by applying a selective-area metalorganic vapor-phase epitaxy technique. Single-electron logic operations using four cooperating single-electron tunneling (SET) transistors has been tested. This logic circuit has an architecture based on a binary decision diagram (BDD) using a Coulomb blockade (CB) in GaAs QDs, which is a representation of digital logic functions using directed graphs. BDD node devices consisting of two SET transistors achieved a two-way path switching operation in single-electron mode due to the CB effects which appeared complementarily in the two SET transistors at 1.9 K. We also demonstrated an AND/NAND operation in a logic circuit by integrating two BDD nodes.

Fabrication of BDD quantum node switches on embedded GaAs quantum wires grown by selective MBE

In view of applications to hexagonal binary decision diagram (BDD) LSIs, a first attempt is made to form quantum BDD node switches on selectively grown (SG) embedded quantum wires (QWRs) by molecular beam epitaxy (MBE). SG branch switches controlled by a Schottky wrap gate (WPG) were successfully fabricated by MBE growth and subsequent device processing. Gate control characteristics were studied by gate-dependent Shubnikov–de-Haas measurements, and the behavior was found to be similar to that of devices fabricated on wires by etching. The switch exhibited clear conductance quantization at low temperature, and temperature dependence of the voltage slope of conductance jump was clarified. A Y-branch BDD node device using two SG branch switches was successfully fabricated, and realized clear path switching characteristics.

Fabrication of GaAs-based integrated half and full adders by novel hexagonal BDD quantum circuit approach

Feasibility of a novel hexagonal binary decision diagram (BDD) quantum circuit approach based on Schottky wrap gate (WPG) control of GaAs/AlGaAs hexagonal nanowire network has been demonstrated through fabrication of half adders and full adders. Quantum BDD node devices were designed and realized utilizing WPG-controlled quantum wire (QWR) and single electron switches. BDD half sum and carry elements of a half adder were fabricated by integrating the WPG BDD node devices and they operated correctly through either quantum transport at low temperature or many electron classical transport at room temperature. Successful design of hexagonal BDD full adders for arbitrary bits on a hexagonal network without nanowire crossover and fabrication of QWR-based BDD 2-bit full adder on the AlGaAs/GaAs etched hexagonal nanowire network with node density of 10 7 cm −2 clearly indicated the capability of the present approach for large scale quantum device integration.

Novel Quantum Wire Branch-Switches for Binary Decision Diagram Logic Architecture Utilizing Schottky Wrap-Gate Control of GaAs/AlGaAs Nanowires

A novel binary decision diagram (BDD) node device based on wrap-gate (WPG) control of AlGaAs/GaAs nanowires is described and fabricated, and its basic operation is characterized. The node device consists of one entry-nanowire branch and two exit-nanowire branches where each of two exit-branches is switched by a Schottky WPG in a complimentary fashion so as to realize path switching for electrons. Basic branch switches as well as BDD node devices were fabricated on AlGaAs/GaAs nanowires formed by electron beam lithography and wet chemical etching of molecular beam epitaxy (MBE)-grown heterostructures. A detailed analysis of gate control characteristics was carried out by magnetotransport measurements. A three-dimensional potential simulation showed that Fermi level pinning on the semiconductor free surface should be carefully taken into consideration for accurate device design. The branch-switch exhibited excellent gate control from low temperatures up to room temperature, showing clear conductance quantization at low temperatures. The fabricated BDD node device realized clear path switching from low temperatures up to room temperature.

GaAs and InGaAs single electron hexagonal nanowire circuits based on binary decision diagram logic architecture

The feasibility of a novel approach for single electron quantum LSIs (Q-LSIs) is investigated. It is based on the binary decision diagram (BDD) logic architecture, using arrays of GaAs and InGaAs single electron BDD node devices formed on hexagonal nanowire networks. Single electron branch switches using nanometer-scale Schottky wrap gates on AlGaAs/GaAs etched nanowires and on InGaAs nanowires by selective MBE growth were fabricated. They showed clear conductance oscillation characteristics controlled by a single electron lateral resonant tunneling. Successful design and fabrication of GaAs-based single electron BDD node devices and circuits including OR logic elements and a 2 bit adder indicates the basic feasibility of realizing single electron Q-LSIs by the novel approach.

III–V quantum devices and circuits based on nanoscale Schottky gate control of hexagonal quantum wire networks

The concept, the present status, key issues and future prospects of a novel hexagonal binary decision diagram (BDD) quantum circuit approach for III–V quantum large-scale integrated circuits (QLSIs) are presented and discussed. In this approach, the BDD logic circuits are implemented on III–V semiconductor-based hexagonal nanowire networks controlled by nanoscale Schottky gates. The hexagonal BDD QLSIs can operate at delay-power products near the quantum limit in the quantum regime as well as in the many-electron classical regime. To demonstrate the feasibility of the present approach, GaAs Schottky wrap gate (WPG)-based single-electron BDD node devices and their integrated circuits were fabricated and their proper operations were confirmed. Selectively grown InGaAs sub-10 nm quantum wires and their hexagonal networks have been investigated to form high-density hexagonal BDD QLSIs operating in the quantum regime at room temperature.

Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires

Previously quantum device research has been done on discrete device levels and lacks a clear vision for high density integration. This paper proposes a new, simple and realistic approach for quantum large scale integrated circuits (QLSIs) where a binary-decision diagram (BDD) logic architecture is implemented by BDD node devices based on quantum wire transistors (QWTrs) and single electron transistors (SETs) realized by the Schottky in-plane gate (IPG) and wrap-gate (WPG) control of III–V hexagonal nanowire networks. To investigate the feasibility of the proposed approach, BDD devices having QWTrs were formed on GaAs/AlGaAs etched nanowire patterns. They showed expected complimentary quantized conductance switching as required to achieve operation at delay-power products near the quantum limit. The use of embedded InGaAs honeycomb wire networks grown by selective MBE on InP substrates is proposed for constructing circuits operating in quantum regime at room temperature.