Bilayer Tunnel Field-effect Transistor Research Articles

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Investigation of the dielectrically modulated electron hole bilayer tunnel field effect transistor for biomolecule detections

This work investigates a Dielectrically Modulated Electron-Hole Bilayer Tunnel Field Effect Transistor (DM-EHBTFET) architecture for biosensing applications using extensive numerical device simulation. The proposed DM-EHBTFET structure incorporates extended source and drain pockets in the channel to ensure vertical band-to-band tunneling (BTBT) dominated transduction. The underlying device physics and sensing performance of the proposed DM-EHBTFET has been comprehensively analyzed based on the tunneling length sensitivity and drain current sensitivity, respectively. Finally, an extensive comparative performance study has been undertaken against conventional lateral tunneling (LT) and vertical tunneling (VT) based DMTFETs, as well as reported state-of-art DMTFETs and DMFETs. The results demonstrate that the optimized DM-EHBTFET outperforms both conventional LT-/VT- DMTFETs with more than 500 times and 150 times improvements in sensitivity, respectively, over a range of biomolecule specifications, and more than 100 times sensitivity improvement has been observed in DM-EHBTFET over reported DMFETs/DMTFETs for lower biomolecule dielectric constant.

Charge-plasma based symmetrical-gate complementary electron–hole bilayer TFET with improved performance for sub-0.5 V operation

In this paper, the complementary charge-plasma (CP) based symmetrical-gate electron–hole bilayer (EHB) tunnel field-effect transistor (TFET) at a low operating voltage (⩽0.5 V) is introduced. Where, by using CP technique, the source/drain and EHB-channel is induced by depositing metal electrode with appropriate work function. Moreover, the immunity against random dopant fluctuations and the feasibility of a self-aligned process due to a symmetrical top/bottom gate arrangement without the need for a high thermal annealing process make the fabrication of the proposed EHB-TFET very reliable and efficient. Moreover, by implementing the density gradient quantum correction model, the quantum confinement and its effect on confining the 2D electron–hole concentration are also corrected as the proposed device has a smaller channel thickness of 5 nm. The proposed device shows superior performance against almost all Si-based CP-TFETs with a higher ON-current of 47.33 μA μm−1, a smaller average subthreshold swing of 13.53 mV dec−1 and a high ON-current to OFF-current ratio of 2.16 × 1013. This indicates that the proposed device is a promising candidate for future low-power applications.

OFF-State Leakage Suppression in Vertical Electron-Hole Bilayer TFET Using Dual-Metal Left-Gate and N+-Pocket.

In this paper, an In0.53Ga0.47As electron–hole bilayer tunnel field-effect transistor (EHBTFET) with a dual-metal left-gate and an N+-pocket (DGNP-EHBTFET) is proposed and systematically studied by means of numerical simulation. Unlike traditional transverse EHBTFETs, the proposed DGNP-EHBTFET can improve device performance without sacrificing the chip density, and can simplify the manufacturing process. The introduction of the dual-metal left-gate and the N+-pocket can shift the point-tunneling junction and adjust the energy band and the electric field in it, aiming to substantially degrade the OFF-state current (IOFF) and maintain good ON-state performance. Moreover, the line tunneling governed by the tunneling-gate and the right-gate can further regulate and control IOFF. By optimizing various parameters related to the N+-pocket and the gate electrodes, DGNP-EHBTFET’s IOFF is reduced by at least four orders of magnitude, it has a 75.1% decreased average subthreshold swing compared with other EHBTFETs, and it can maintain a high ON-state current. This design greatly promotes the application potential of EHBTFETs.

Modeling of InAs/Si Electron-Hole Bilayer Tunnel Field Effect Transistor

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Theoretical Study of Current-Voltage Characteristics of Electron-Hole Bilayer Tunnel Field Effect Transistors of Different Channel Semiconductors

Theoretical Study of Current-Voltage Characteristics of Electron-Hole Bilayer Tunnel Field Effect Transistors of Different Channel Semiconductors

Impact of Switching Voltage on Complementary Steep-Slope Tunnel Field Effect Transistor Circuits

Impacts of switching voltage of a bilayer tunneling field-effect transistor (TFET) with extremely small subthreshold swing on energy consumption in static and dynamic circuits are investigated in this study. The TFET circuit simulation under an operating voltage of 0.3 V is performed by the simulation program with integrated circuit emphasis (SPICE) into which electrical characteristics of the n- and p-channel bilayer TFETs calculated by device simulation are introduced. The static simulation of an inverter has clarified that the adjustment of the OFF-state voltage ( ${V}_{{ \mathrm{\scriptscriptstyle OFF}}}{)}$ , defined as a gate voltage at a drain current of $10^{{-{11}}}$ A/ $\mu \text{m}$ , to 0.08–0.14 V can be effective to suppress the short-circuit current. In contrast, when ${V}_{ \mathrm{\scriptscriptstyle OFF}}$ of the TFET is made close to 0 V according to the conventional manner of the ${V}_{ \mathrm{\scriptscriptstyle OFF}}$ adjustment, the energy consumption of the TFET inverter significantly increases because of the short-circuit leakage current. It is clarified from the dynamic simulation of a 11-stage ring oscillator (RO) that, as a result of this ${V}_{ \mathrm{\scriptscriptstyle OFF}}$ adjustment, the energy consumption of the TFET RO is comparable or even lower under high load capacitance than that of complementary metal–oxide–semiconductor (CMOS) RO, because of reduction in leakage current at a small expense of increase in the delay time. The present examination on ${V}_{ \mathrm{\scriptscriptstyle OFF}}$ adjustment can provide a new guideline of device design not only for TFETs but also for other steep-slope switching devices for future low-power internet-of-things (IoT) applications.

Design and performance optimization of thin film tin monoxide (SnO)/silicon electron–hole bilayer tunnel field-effect transistor

This paper presents a novel thin film electron–hole bilayer tunnel field-effect transistor based on an oxide semiconductor tin monoxide (SnO)/silicon heterojunction (TFBTFET), which delivers low-power high switching speed characteristics. SnO has an intrinsic p-type profile, which provides desirable properties for application in thin film tunnel transistors and liquid crystal displays. Unlike conventional tunnel field-effect transistors with limited horizontal tunneling direction, the tunneling window of the TFBTFET is created along the channel length in the vertical direction, leading to significantly increased drain drive current. The results demonstrate that the steep transition of the current from off-state to on-state delivers subthreshold swing of 5 mV/dec with on-state current of 3.03 × 10−5 (A/µm), off-state current of 5.1 × 10−14 (A/µm) and on/off current ratio of 5.94 × 108. The impact of critical scaling of design parameters on the electrical performance of the device is comprehensively investigated by calculating the coefficient of variation (CV), expressed as a percentage, of the main electrical measures. The 2D variation contour of required voltage for the onset of band-to-band tunneling is computed as a function of the top and bottom gate work function to determine an optimum value yielding superior electrical performance. Moreover, CV analysis reveals that the off-state current and subthreshold swing are relatively insensitive to the variation in gate length, which indicates the potential for application of the device in integrated circuits with superior efficiency.

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

Modeling the Current–Voltage Characteristics of Ge₁₋ₓSnₓ Electron–Hole Bilayer TFET With Various Compositions

In this article, we present, for the first time, the results of simulation and analysis of the current-voltage characteristics of germanium-tin electron-hole bilayer tunnel field-effect transistor (EHB TFET) of various compositions of the semiconductor substrate. Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> is an interesting material due to the possibility of tuning the band structure by changing the Sn content. The direct and indirect bandgap of GeSn can be changed to affect the direct and phonon-assisted band-to-band tunneling currents. In this article, both currents are calculated for various compositions of Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> and the channel body thickness as a parameter. The simulated structure exhibits steep-slope current-voltage characteristics due to the reduced carrier dimensionality and the use of 2-D-2-D tunneling as the transport mechanism. Sudden current bumps on characteristics are related to the alignment of the subsequent hole and electron energy levels in the gate-induced surface quantum wells. An increase in the Sn content results in a boost of the ON-current, which is related to the higher magnitude of the direct tunneling current. This effect depends strongly on the body thickness. We show that the application of GeSn in EHB TFET structure can be beneficial in terms of low-power applications.

Source engineering for bilayer tunnel field-effect transistor with hetero tunnel junction: thickness and impurity concentration

We have investigated the impacts of source layer thickness, source impurity concentration and channel thickness in a bilayer tunneling field-effect transistor with a thin-film hetero tunneling junction on electrical characteristics. Device simulation has revealed that thinning of the source layer significantly degrades on-state current (Ion) due to non-uniform band-to-band tunneling over the tunneling junction, while channel layer thinning is effective for increasing Ion. On the other hand, source/channel impurity concentrations of around 3 × 1018 cm‒3 are found to be optimal for high Ion, high Ion/Ioff and suppression of transfer characteristic shifts with changing Vd.

Improvement in Electrical Characteristics of ZnSnO/Si Bilayer TFET by W/Al₂O₃ Gate Stack

We have examined impacts of gate insulator (Al2O3 or HfO2) and gate electrode (TiN or W) on electrical performance of ZnSnO/Si bilayer tunneling fieldeffect transistors (TFETs). It is found from the capacitance-voltage ( ${C}$ - ${V}$ ) characteristics that the W gate is effective to reduce the counter-clockwise hysteresis. Additionally, the optimal temperature of post-metallization annealing (PMA) is different for each gate stack, and this optimization is critically important for the high ON-state current ( ${I} _{\mathrm{ ON}}$ ) and steep ON/OFF switching. The W/Al2O3/ZnSnO/Si bilayer TFET provides the hysteresis-free steep ON/OFF switching with the minimum sub-threshold swing ( SS ) of 65.4 mV/dec. and average SS of 72.0 mV/dec. in a gate-voltage swing of 0.3 V, which are 19% and 18% lower than the control TiN/Al2O3/ZnSnO/Si bilayer TFET. When the gate stack is replaced by W/HfO2/Al2O3, the TFET exhibits less steep ON/OFF switching in spite of thinning capacitance equivalent thickness (CET) from 5.9 and 2.3 nm. These results indicate the importance of improvement in the gate stack quality on the sub-threshold characteristics of the bilayer TFETs.

Group IV Based Bi-Layer Tunneling Field Effect Transistor

We have proposed and demonstrated bi-layer tunneling FETs (TFETs) composed of group IV/oxide semiconductor type-II heterojunctions, where the group IV and oxide semiconductors work as source and channels, respectively, of TFETs. The simulation study has revealed that ZnO/Si or Ge TFETs can exhibit extremely-steep sub-threshold slope of ~ 1 mV/dec with Ion of ~100 μA/μm order. The operation of bi-layer ZnO(ZnSnO)/Ge(Si) TFETs has been experimentally demonstrated with a minimal sub-threshold slope of 71 mV/dec at room temperature.

Performance optimization of a nanoscale GaSb P-channel electron-hole bilayer tunnel field effect transistor using metal gate workfunction engineering

In this paper, the electrical characteristics of a double gate P-channel GaSb Electron-Hole Bilayer Tunnel Field Effect Transistor (EHBTFET) is comprehensively investigated and impact of main design parameters on the performance of the device is thoroughly assessed. The corresponding low carrier effective mass of GaSb provides high probability of tunneling current that eventually exhibits an improvement in the on-state current and subthreshold swing (SS). The results reveal that unlike the conventional tunnel field effect transistor (TFET) in which band to band tunneling current occurs horizontally from source to channel, the tunneling junction in EHBTFET is electrically created in the intrinsic channel in the entire region of the gate overlap length along the vertical direction. Due to the expanding of the tunneling area, the on-state current of EHBTEFT is increased five order of magnitude in comparison with lateral TFET and subthreshold swing of SS = 2 mV dec−1 with on/off current ratio of 2.5 × 1011 is achieved. The top and bottom gate workfunction are critical design parameters that fundamentally affect the tunneling rate. The 2D variation matrix of threshold voltage and on-state current are calculated as a function of top and bottom gate workfunction for optimizing the device performance. In addition, a comprehensive sensitivity analysis via calculating standard deviation and mean value of main electrical parameters are assessed to evaluate the susceptibility of device performance with respect to the variation of design parameters. The main feature of this device is the insensitivity of the tunneling rate to the source doping density that solves the problem of low solubility of dopants in III-V materials. Moreover, subthreshold swing and off-state current and are not affected by the gate length scaling, facilitating the employment of this device in nanoscale regime. The results in this paper pave the way for designing low power steep-slope logic circuits.

ZnO/Si and ZnO/Ge bilayer tunneling field effect transistors: Experimental characterization of electrical properties

In this study, we experimentally characterize the electrical properties of a bilayer tunneling field effect transistor (TFET) with a heterotunneling junction composed of an oxide-semiconductor source and a group-IV-semiconductor channel in detail. Bilayer TFETs with a n-ZnO/p-Si or n-ZnO/p-Ge heterotunneling junction with type-II energy band alignment are fabricated by pulsed-laser deposition of a zinc oxide (ZnO) layer on Si or Ge with various impurity concentrations. The evidence of the TFET operation are examined through a comparison of the electrical characteristics with ZnO thin film transistors as well as the tunneling junction area dependence, which is important for clarifying the operating mechanism. The source material and its impurity concentration significantly affect the Id-Vg and Id-Vd characteristics of the bilayer TFETs, with reducing tunneling barrier height and tunneling distance. The influence of the source materials and doping concentrations is also studied by simulation. As a result, the minimum subthreshold swing (SS) of 71 mV/dec and the Ion/Ioff ratio of ∼6 × 108 have been achieved for n-ZnO/p-Si and n-ZnO/p-Ge TFETs, respectively, at room temperature. It is also found that the fabricated TFET shows weak measurement temperature dependencies of Ion and SS, which are expected for TFETs, with the extremely low off-state current in a fA/μm range. These characterizations of the electrical characteristics of the bilayer TFETs are important not only for a physical understanding of the operating mechanism but also for further improvement of the TFET performance.

Performance investigation of steep-slope core–shell nanotube indium nitride electron–hole bilayer tunnel field effect transistor

In this paper, the effects of main physical and structural parameters on the electrical characteristics of indium nitride core–shell nanotube electron–hole bilayer tunnel field effect transistor (NEHBTFET) are comprehensively investigated via simulation study for optimizing the device performance. The proposed structure offers excellent band to band tunneling efficiency and steeper turn-on drain current by providing the tunneling junction normal to the gate electric field between the region of outer shell gate and inner core gate. The simulation results reveal that the on-state current and subthreshold swing of NEHBTFET are greatly improved via expanding the band to band tunneling area along the channel and in the vertical direction in comparison with conventional nanowire TFET with narrow lateral source–channel tunneling junction. The n+–p+ tunneling junction is created electrically in the intrinsic region and a framework of core and shell gate work function engineering are conducted via calculating 2D variation matrix of the on-state current and threshold voltage for optimizing the device performance. The sensitivity of device’s main electrical parameters with respect to the variation of device physical and geometrical parameters reveals that the electrical parameters are highly insensitive to the source doping density which solves the major challenge of low solubility of dopants in III-nitride devices. In addition, the off-state current and subthreshold swings are not affected by the gate length scaling that is an indication of feasibility of this device in nanoscale regime.

Bilayer tunneling field effect transistor with oxide-semiconductor and group-IV semiconductor hetero junction: Simulation analysis of electrical characteristics

Operation mechanisms and electrical characteristics of tunneling field-effect transistors (TFETs) employing a hetero tunneling junction by utilizing an n-type oxide-semiconductor (OS) and a p-type group-IV-semiconductor are comprehensibly analyzed. Gate-normal band-to-band tunneling (BTBT) has high potential for the superior TFET performance such as high on-state current and small sub-threshold swing (S.S.). Additionally, a hetero tunneling junction with type-II energy band alignment is promising to exponentially increase tunneling probability with keeping small off-state current. Therefore, in this study, we investigate the impact of key material and device parameters such as energy band alignment of source/channel regions and thickness of the OS channel layer or gate insulator based on technology computer aided design (TCAD) simulation. The gate-controlled uniform band bending along the source-drain direction realizes uniform BTBT in the entire region of the hetero tunneling junction. Also, the reduction of the tunneling barrier height, which is continuously controlled by the conduction band minimum of the OS-channel and the valence band maximum of the IV-source, is effective to increases on-state current and decrease S.S. value. On the other hand, the thicknesses of OS channel layer and gate insulator have strong influences on tunneling probability and threshold voltage. Therefore, the sub-threshold characteristics of TFETs are sensitive to non-uniformities in the tunneling junction such as channel thickness fluctuation and surface potential fluctuation at the metal-oxide-semiconductor (MOS) interfaces. These numerical analyses of the device operation are essentially important to understand the effects of key device parameters on the TFET performance and to realize the superior electrical performance.

Fabrication and Electrical Characteristics of ZnSnO/Si Bilayer Tunneling Filed-Effect Transistors

We demonstrate improvement of electrical characteristics of a bilayer tunneling field effect transistor (TFET) composed of an n-type zinc-tin-oxide (ZnSnO) channel with superior thickness uniformity and a p-type Si source. Careful optimization of the deposition condition of the ZnSnO layer leads to the significant improvement of the thickness uniformity thanks to its amorphous structure. It is promising to reduce the average sub-threshold swing ( ${S}$ . ${S}$ .) of the bilayer TFET. The average ${S}$ . ${S}$ . of the amorphous ZnSnO/Si TFET is 87 mV/dec. in a gate voltage swing of 0.3 V, which is lower by 30% than that of the poly-crystalline ZnO/Si TFET with the rough surface. The minimum ${S}$ . ${S}$ . value of 80 mV/dec. in the ZnSnO/Si TFET is similar to that in the ZnO/Si TFET. Additionally, the ZnSnO/Si TFET has realized the increase in on-state current ( ${I} _{\mathrm{ on}}$ ) and the achieved ${I} _{\mathrm{ on}}$ of 1.7 $\mu \text{A}/\mu \text{m}$ is approximately 8 times higher than that of the ZnO/Si TFET. We also found that the ZnSnO/Si TFET shows the stronger temperature dependence of both ${I} _{\mathrm{ on}}$ and ${S}$ . ${S}$ . than the ZnO/Si TFET. These differences in the electrical characteristics between ZnSnO and ZnO TFETs are discussed in terms of the amorphous and ploy-crystalline natures of the OS channels.

Gate Leakage Tunneling Impact on the InAs/GaSb Heterojunction Electron–Hole Bilayer Tunneling Field-Effect Transistor

Among the different types of bilayer tunneling field-effect transistors exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, the utilization of InAs/GaSb channels proves to be an appealing means to enhance ON-current levels. Ultrathin channel thicknesses make quantum confinement be the agent that closes the broken gap of the InAs/GaSb heterojunction leading to a staggered gap which blocks the tunneling current in the OFF state. In this paper, the gate leakage tunneling current is analyzed as one of the main critical processes degrading the performance of the proposed structure. Appropriate gate stacks of HfO2/Al2O3 combined with gate-to-drain underlaps are shown to effectively suppress this leakage tunneling, while at the same time, preserve an adequate electrostatic control over the channel. Simulation results for the most optimized configurations feature ON-state levels of up to $400\mu \text{A}/\mu \text{m}$ and subthreshold swings of $\approx 3$ mV/dec over more than 7 decades of current.

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with $$\hbox {M}_{1}$$ as overlap gate, $$\hbox {M}_{2}$$ as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio is increased by more than one order at $$V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0$$ V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps ( $$\hbox {Lgs}\ne \hbox {Lgd}$$ ) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of $$0.23~\upmu \hbox {A}/\upmu \hbox {m}$$ (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}$$ (two orders higher) is achieved at $$V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}$$ in the proposed structure 2 in comparison with the conventional one.