Bidirectional Bus Research Articles

I2C master RTL development using Verilog HDL and verification using UVM

The objective of the project is to develop the I2C Master RTL using VHDL and verify it using UVM. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices, suitable for short-distance communication between multiple devices. The I2C Master facilitates communication between the Core and various slaves in the chip. The I2C Master IP implemented here is a subset of the full I2C protocol, as some features are not supported. The RTL design of I2C is open source, and its functional verification is performed using System Verilog and UVM. The Universal Verification Methodology was developed to provide a well-structured and reusable verification environment without interfering with the device under test (DUT). This paper highlights the reusability of I2C using UVM, details the construction of the verification environment, and describes the implementation of test cases for this protocol. Additionally, the performance metrics and verification coverage results are discussed, demonstrating the efficiency and robustness of the developed environment. The results show significant improvements in verification time and accuracy, validating the approach.

I2C Master Scan Chain Insertion and Functional Coverage

I2C is a serial, bidirectional bus for communication that Philips Semiconductors created. only two bus lines are needed a (SDA) serial data line and a (SCL) serial clock line. With the addition of scan chains, a method for I2C Bus testing has been implemented in this study. In order to achieve the necessary requirements, the number of scan chain insertions is predetermined. The coverage of the Functions is also performed to verify the test bench. Keywords: I2C, Scan Chain, Coverage, Testing, Design for test

Unified Virtual Oscillator Control for Grid-Forming and Grid-Following Converters

A unified virtual oscillator controller (uVOC) is proposed, which enables a unified analysis, design, and implementation framework for both grid-forming (GFM) and grid-following (GFL) voltage-source converters (VSCs). Oscillator-based GFM controllers, such as dispatchable virtual oscillator control (dVOC), offer a rigorous analytical framework with enhanced synchronization but lack effective fault handling capability, which severely limits practical application. The proposed uVOC facilitates synchronization with an arbitrarily low grid voltage and fast overcurrent limiting; this enables effective fault ride-through unlike existing GFM controllers which typically switch to a back-up controller during the fault. GFM operation with uVOC is achieved in both grid-connected and islanded modes with seamless transitions between the two. In GFL converters, bidirectional power flow control and dc bus voltage regulation are achieved with uVOC. No phase-locked loop (PLL) is required for either GFL or GFM operation circumventing the synchronization issues associated with PLLs in weak grid applications. Detail small-signal models for GFM and GFL operation have been developed, and the systematic design guidelines for controller parameters are provided. The proposed controller is validated through hardware experiments in a hybrid ac-dc microgrid.

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing

We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A72 processor cores operating at 4.0 GHz. A bidirectional mesh bus with 2-mm flop-to-flop distance is distributed throughout the chiplet for high-speed on-die data transport above 4.0 GHz. The chiplets communicate with each other through ultrashort reach (0.5 mm long) interposer channels using a Low-voltage-In-Package-INterCONnect (LIPINCON) clock-forwarded parallel interface. The scalable link module offers 320 GB/s of aggregate bandwidth, operating at 8.0 Gb/s/pin and 0.3-V transmitter swing without receiver termination to achieve 0.56-pJ/bit energy efficiency and 1.6-Tb/s/mm2 bandwidth density. Measurements of the fabricated SiP validate the functionality and performance of the cores, on-die data bus, and inter-chiplet link. The built-in LIPINCON eye-scan feature validates inter-chiplet connectivity at 8.0 Gb/s with an eye opening of 244 mV and 0.69 UI.

On Bidirectional DC Nano-Grids: Design Considerations and an Architecture Proposal

The use of DC distribution networks has several advantages, especially for energy saving and integration of energy storage system and renewable energies. In this regard, DC nano-grids are a very interesting solution when distributing electrical power in households. In this paper, an analysis about the possible bidirectional capability of this DC nano-grid is presented. The end-user can freely connect either a passive load (demanding power) or an active one (able to sink current to the grid). The analysis is divided into three different parts. First, a discussion about the most promising power architecture is addressed, taking into consideration the loads in a house. Second, a standard for voltage regulation in a bidirectional DC nano-grid is proposed. Finally, a possible bus provider for this particular bidirectional DC nano-grid is also addressed. This power converter is based on a Dual Active Bridge cascaded with five synchronous buck converters. The key design aspects of the proposed topology are analyzed to emphasize the particular constraints imposed by the standard and the power architecture. A 500 W, 380 V to 24 V bidirectional bus provider has been built in order to experimentally validate the standard proposal and the design aspects.

Virtual Resistor-Based Integrated DC Bus Voltage Conditioner for Stability Improvement of Cascaded Power Converters

A bidirectional integrated bus voltage conditioner (IBVC) for an isolated phase-shifted full bridge (PSFB) dc/dc converter is proposed to reduce the dc bus voltage oscillations in a cascaded power converter system, where a load converter is controlled tightly with high-control bandwidth. In the proposed method, unlike conventional dc bus voltage stabilization methods for which auxiliary switches are used, the multiplexing utilization of the full bridge switches at the primary side of a PSFB is adopted. In this paper, to improve the dc bus voltage stability, an equivalent virtual resistor is implemented by applying the duty cycle regulation for both legs of the PSFB. The effectiveness of the proposed method on the dc voltage stabilization is examined through simulations and experiments. The achieved results reveal that the dc bus voltage stability is significantly improved with the proposed method.

MINIMIZING USER AND OPERATOR COSTS OF SINGLE LINE BUS SERVICE USING OPERATIONAL STRATEGIES

This work presents a methodology for minimizing costs involved in the operation of a single line bus service. The model developed is based on optimal implementation of operational strategies tailored to passenger demand for a bi-directional single bus line. As a result, the commonly used timetable for Full Route Operation (FRO) will have to change to accommodate three types of strategies: short turn, limited stop, and mixed strategy (a combination of short turn and limited stop). The use of operational strategies will better match supply and demand, and will thus improve operation efficiency. The optimization model determines which trips of the given FRO timetable will be implemented with given strategies considering the trade-offs between passenger and operator costs. Moreover, in applying the model, the availability of real time information for passengers is considered in the calculation of waiting times. The proposed model is interpreted in the context of a small example, which serves as an explanatory devise. Then, it is applied to a real life case study in Dalian, China. The results show an indication that a significant saving could be attained by the use of multiple strategies. These savings were especially observed in the reduction of operational costs involved with the saving of travel times and running empty seats.

Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system

This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT.

Bus Operations Scheduling Subject to Resource Constraints Using Evolutionary Optimization

In public transport operations, vehicles tend to bunch together due to the instability of passenger demand and traffic conditions. Fluctuation of the expected waiting times of passengers at bus stops due to bus bunching is perceived as service unreliability and degrades the overall quality of service. For assessing the performance of high-frequency bus services, transportation authorities monitor the daily operations via Transit Management Systems (TMS) that collect vehicle positioning information in near real-time. This work explores the potential of using Automated Vehicle Location (AVL) data from the running vehicles for generating bus schedules that improve the service reliability and conform to various regulatory constraints. The computer-aided generation of optimal bus schedules is a tedious task due to the nonlinear and multi-variable nature of the bus scheduling problem. For this reason, this work develops a two-level approach where (i) the regulatory constraints are satisfied and (ii) the waiting times of passengers are optimized with the introduction of an evolutionary algorithm. This work also discusses the experimental results from the implementation of such an approach in a bi-directional bus line operated by a major bus operator in northern Europe.

Optical Beam Propagation and Ray Tracing Simulation of Interruption-Free Asymmetric Multimode Bus Couplers

In this article, we present a coupling concept for an interruption-free asymmetric bidirectional optical bus coupler for board and module level. With this approach, it is possible to connect several electro-optical devices to a single waveguide. A core-to-core connection principle is used, where the cores get into physical contact at their side faces. The coupling ratio can be tuned by adjusting the overlap area of the two cores with different contact pressures. Because of a bending in one of the waveguides, it is possible to achieve a specific asymmetric coupler design, where the coupling ratio depends on the coupling direction (bent waveguide to rigid one or vice versa). To derive design rules for prototyping, a simulation is performed using two different independent approaches for cross-checking. With a ray tracing simulation, coupling ratios and energy distribution within the bent core are analyzed. In addition, a simulation with the beam propagation method is used to take wave optical effects into account as well as to establish a holistic view on the coupling concept.

Determining Optimal Strategies for Single-Line Bus Operation by Means of Smartphone Demand Data

Passenger demand along an urban bidirectional bus line is usually neither uniform nor symmetric. In practice, buses are operated along such routes without efficient use of operational routing-related strategies. This work focused on the design of two routing-related strategies, given that fluctuating passenger demand could be estimated with the use of smartphones. In this way, a better match between supply and demand can be attained, and the operational cost involved can be reduced. Optimization formulation was used in this work for the design of routing changes through four possible strategies: full-route operation, short-turn, limited-stop, and a combination of the latter two strategies. The objective function was to minimize the fleet size required to handle the expected demand comfortably by using the onboard loading criterion. This is a practical objective, especially from the operator’s perspective. The expected origin–destination demand of a single bus line was constructed on the basis of the existing demand data and potential changes in demand, given service improvement in travel time, waiting time, and seat availability. The potential demand, whether overt or obscure, was assumed to be determinable with the use of smartphone apps, including online service information. A detailed example is used as an expository device for explaining the methodology developed, along with a case study from Dalian, China. The results of the case study show that, by applying the proposed methodology, the fleet size of the single-line bus operation can be reduced by four buses on the basis of the anticipated passenger demand.

B-Planner: Planning Bidirectional Night Bus Routes Using Large-Scale Taxi GPS Traces

Taxi GPS traces can inform us the human mobility patterns in modern cities. Instead of leveraging the costly and inaccurate human surveys about people's mobility, we intend to explore the night bus route planning issue by using taxi GPS traces. Specifically, we propose a two-phase approach for bidirectional night bus route planning. In the first phase, we develop a process to cluster “hot” areas with dense passenger pick up/drop off and then propose effective methods to split big hot areas into clusters and identify a location in each cluster as a candidate bus stop. In the second phase, given the bus route origin, destination, candidate bus stops, and bus operation time constraints, we derive several effective rules to build the bus route graph and prune invalid stops and edges iteratively. Based on this graph, we further develop a bidirectional probability-based spreading algorithm to generate candidate bus routes automatically. We finally select the best bidirectional bus route, which expects the maximum number of passengers under the given conditions and constraints. To validate the effectiveness of the proposed approach, extensive empirical studies are performed on a real-world taxi GPS data set, which contains more than 1.57 million night passenger delivery trips, generated by 7600 taxis in a month.

Optimized FFT computations on heterogeneous platforms with application to the Poisson equation

We develop optimized multi-dimensional FFT implementations on CPU–GPU heterogeneous platforms for the case when the input is too large to fit on the GPU global memory, and use the resulting techniques to develop a fast Poisson solver. The solver involves memory bound computations for which the large 3D data may have to be transferred over the PCIe bus several times during the computation. We develop a new strategy to decompose and allocate the computation between the GPU and the CPU such that the 3D data is transferred only once to the device memory, and the executions of the GPU kernels are almost completely overlapped with the PCI data transfer. We were able to achieve significantly better performance than what has been reported in previous related work, including over 145 GFLOPS for the three periodic boundary conditions (single precision version), and over 105 GFLOPS for the two periodic, one Neumann boundary conditions (single precision version). The effective bidirectional PCIe bus bandwidth achieved is 9–10 GB/s, which is close to the best possible on our platform. For all the cases tested, the single 3D data PCIe transfer time, which constitutes a lower bound on what is possible on our platform, takes almost 70% of the total execution time of the Poisson solver.

IMPLEMENTATION OF USB TRANSCEIVER MACROCELL INTERFACE

The universal serial bus (USB) transceiver macro cell interface (UTMI) is a two wire, bi-directional serial bus interface. UTMI consists of transmitting and receiving sections, in which the transmitter of the UTMI sends data to different USB devices through D+ and Dlines whereas the receiver gets data on the same lines. UTMI is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. There are three functional blocks present in USB controller; those are Serial Interface Engine (SIE), UTMI and Device Specific Logic (DSL). The parallel data from SIE is taken into the transmit hold register and this data is sent to transmit shift register from where the data is converted serially. This serial data is bit stuffed to perform data transitions for clock recovery and NRZI (1) encoding. Then the encoded data is sent on to the serial bus. When the data is received on the serial bus, it is decoded, bit unstuffed and is sent to receive shift register. After the shift register is full, the Data is sent to receive hold register. This presentation reveals the FPGA implementation of UTMI transmission rate providing with USB 2.0 specifications. Further UTMI has been designed by using VHDL code and simulated, synthesized and programmed to the targeted Spartan family of FPGA in the Xilinx environment.

Photolithography-free polymer optical waveguide arrays for optical backplane bus

In this paper, an innovative 3-to-3 bi-directional optical bus architecture based on multimode polymer waveguides with embedded 45° micro-mirrors was successfully demonstrated. With a lithography-free imprinting process by high quality electroplated metallic mold, the device can be precisely replicated with a low fabrication cost. Superior to any point-to-point optical waveguide, the implemented optical bus structure is capable of broadcasting and receiving high speed data at 10 Gbit/sec among multiple points as a high performance optical backplane.

Development of a composite line source emission model for traffic interrupted microenvironments and its application in particle number emissions at a bus station

A composite line source emission (CLSE) model was developed to specifically quantify exposure levels and describe the spatial variability of vehicle emissions in traffic interrupted microenvironments. This model took into account the complexity of vehicle movements in the queue, as well as different emission rates relevant to various driving conditions (cruise, decelerate, idle and accelerate), and it utilised multi-representative segments to capture the accurate emission distribution for real vehicle flow. Hence, this model was able to quickly quantify the time spent in each segment within the considered zone, as well as the composition and position of the requisite segments based on the vehicle fleet information, which not only helped to quantify the enhanced emissions at critical locations, but it also helped to define the emission source distribution of the disrupted steady flow for further dispersion modelling. The model then was applied to estimate particle number emissions at a bi-directional bus station used by diesel and compressed natural gas fuelled buses. It was found that the acceleration distance was of critical importance when estimating particle number emission, since the highest emissions occurred in sections where most of the buses were accelerating and no significant increases were observed at locations where they idled. It was also shown that emissions at the front end of the platform were 43 times greater than at the rear of the platform. Although the CLSE model is intended to be applied in traffic management and transport analysis systems for the evaluation of exposure, as well as the simulation of vehicle emissions in traffic interrupted microenvironments, the bus station model can also be used for the input of initial source definitions in future dispersion models.

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion

Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4% with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes, and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally, the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE. The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average. The proposed algorithm is simple and extremely practical.

Development of a methodology for the quantification of particle number and gaseous concentrations in a bidirectional bus tunnel and the derivation of emission factors

Particle number, NO x and CO concentrations were measured simultaneously at the air entry portal and at the mid-point of a 511 m bidirectional road tunnel, used entirely by urban public transport buses. The aim of this study was to provide information on concentrations of these pollutants inside a unique bus tunnel, and to develop a viable methodology for determining emission factors for on-road vehicles. Measurements were made continuously over a period of five days that included a complete weekend. Traffic flow rate and air flow rate were also monitored. The mean particle number concentration at mid-tunnel was 4.1 × 10 4 cm −3, which was over four times higher than the urban background concentration. The mean concentrations of NO x and CO at mid-tunnel were 464 ppb and 802 ppb, respectively. All these values were between 2 and 4 times higher than at the air entry portal. Median concentrations during selected time segments coinciding with the morning and evening rush hours, mid-day during weekdays and full day during the weekends were determined and the corresponding bus emission factors of each of the three parameters was calculated. Mean emission factors found for particle number, NO x and CO were 7.1 × 10 14 particles km −1, 8.1 g km −1 and 15.9 g km −1, respectively. These values compared well with previous studies, showing that the methodology adopted was sound and viable.

DynaSPOT: Dynamic Services Provisioned Optical Transport Test-Bed—Achieving Multirate Multiservice Dynamic Provisioning Using Strongly Connected Light-Trail (SLiT) Technology

In this paper, we report on the dynamic services provisioned optical transport (DynaSPOT) test-bed-a next-generation metro ring architecture that facilitates provisioning of emerging services such as Triple Play, Video-on-Demand (VoD), pseudowire edge-to-edge emulation (PWE3), IPTV, and Data Center Storage traffic. The test-bed is based on the recently proposed strongly connected light-trail (SLiT) technology that enables the triple features of dynamic provisioning, spatial subwavelength grooming and optical multicasting-that are quintessential for provisioning of the aforementioned emerging services. SLiT technology entails the use of a bidirectional optical wavelength bus that is time-shared by nodes through an out-of-band control channel. To do so, the nodes in a SLiT exhibit architectural properties that facilitate bus function. These properties at the network side include ability to support the dual signal flow of drop and continue as well as passive add, while at the client side include the ability to store data in order to support time-shared access. The latter (client side) improvisation is done through a new type of transponder card-called the trailponder that provides for (electronic) storage of data and fast transmission (burst-mode) onto the SLiT. Further in order to efficiently provision services over the SLiT, there is a need for an efficient algorithm that facilitates meeting of service requirements. To meet service requirements we propose a dynamic bandwidth allocation algorithm that allocates data time-slots to nodes based on a valuation method. The valuation method is principally based on an auctioning scheme whereby nodes send their valuations (bids) and a controller node responds to bids by sending a grant message. The auctioning occurs in the control layer, out-of-band and ahead in time. The novelty of the algorithm is the ability to take into consideration the dual service requirements of bandwidth request, as well as delay sensitivity. At the hardware level, implementation is complex-as our trailponders are layer-2 devices that have limited service differentiation capability. Here, we propose a dual VLAN tag and GFP-based unique approach that is used for providing service differentiation at layer-2. Another innovation in our test-bed is the ability to support multispeed traffic. While some nodes function at 1 Gb/s, and others function at 2.5 Gb/s (using corresponding receivers), a select few nodes can support both 1- and 2.5-Gb/s operation. This novel multispeed support coalesced with the formerly mentioned multiservice support is a much needed boost for services in the metro networks. We showcase the test-bed and associated results, as well as descriptions of hardware subsystems.

An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques

This paper describes a newly developed automatic direction control scheme for bi-directional bus repeaters that uses dynamic collaborative driving techniques. Repeater directions are rapidly determined by detecting the direction of control signal propagation through an additional control signal line that is driven by dynamic collaborative drivers. Application to an on-chip peripheral bus reduces control circuit transistor counts by about 75% and the number of control signal lines by about 50% without loss of speed. Experimental results for a 0.18-μm CMOS implementation indicate that the proposed scheme is four times faster than a conventional scheme with no bi-directional bus reneaters.