I2C master RTL development using Verilog HDL and verification using UVM

Abstract

The objective of the project is to develop the I2C Master RTL using VHDL and verify it using UVM. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices, suitable for short-distance communication between multiple devices. The I2C Master facilitates communication between the Core and various slaves in the chip. The I2C Master IP implemented here is a subset of the full I2C protocol, as some features are not supported. The RTL design of I2C is open source, and its functional verification is performed using System Verilog and UVM. The Universal Verification Methodology was developed to provide a well-structured and reusable verification environment without interfering with the device under test (DUT). This paper highlights the reusability of I2C using UVM, details the construction of the verification environment, and describes the implementation of test cases for this protocol. Additionally, the performance metrics and verification coverage results are discussed, demonstrating the efficiency and robustness of the developed environment. The results show significant improvements in verification time and accuracy, validating the approach.