Bidirectional Bus Research Articles

Automated Bus Generation for Multiprocessor SoC Design

The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call BusSynth, uses this methodology to generate five different bus systems as examples: 1) bidirectional first-in first-out bus architecture; 2) global bus architecture (GBA) version I; 3) GBA version III; 4) hybrid bus architecture (Hybrid); and 5) split bus architecture. We verify and evaluate the performance of each bus system in the context of three applications: an orthogonal frequency division multiplexing wireless transmitter, an MPEG2 decoder, and a database example. Our methodology gives the designer a great benefit in the fast-design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types, and software programming style. In this paper, we show that BusSynth can generate buses that, when compared to a typical general GBA, achieve superior performance (e.g., 41% reduction in execution time in the case of a database example). In addition, the bus architecture generated by BusSynth is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.

The Systolic Reconfigurable Mesh

In this paper, we introduce the Systolic Reconfigurable Mesh (SRM), which combines aspects of the reconfigurable mesh with that of systolic arrays. Every processor controls a local switch that can be reconfigured during every clock cycle in order to control the physical connections between its four bi-directional bus lines. Data is input on one side of the systolic reconfigurable mesh and output from another side, one row/column per unit time. Efficient algorithms are presented for intermediate-level vision tasks, including histograming, connectivity, convexity, and proximity.

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

Single-board computer based control system for a portable Raman device with integrated chemical identification

We report the development of a battery-powered portable chemical identification device for field use consisting of an acousto-optic tunable filter (AOTF)-based Raman spectrometer with integrated data processing and analysis software. The various components and custom circuitry are integrated into a self-contained instrument by control software that runs on an embedded single-board computer (SBC), which communicates with the various instrument modules through a 48-line bidirectional TTL bus. The user interacts with the instrument via a touch-sensitive liquid crystal display unit (LCD) that provides soft buttons for user control as well as visual feedback (e.g., spectral plots, stored data, instrument settings, etc.) from the instrument. The control software manages all operational aspects of the instrument with the exception of the power management module that is run by embedded firmware. The SBC-based software includes both automated and manual library searching capabilities, permitting rapid identification of samples in the field. The use of the SBC in tandem with the LCD touchscreen for interfacing and control provides the instrument with a great deal of flexibility as its function can be customized to specific users or tasks via software modifications alone. The instrument, as currently configured, can be operated as a research-grade Raman spectrometer for scientific applications and as a “black-box” chemical identification system for field use. The instrument can acquire 198-point spectra over a spectral range of 238–1620 cm−1, perform a library search, and display the results in less than 14 s. The operating modes of the instrument are demonstrated illustrating the utility and flexibility afforded the system by the SBC–LCD control module.

A performance and implementation comparison of bidirectional and dual bus 2-D WDM multiple-plane optical interconnections with row-column multihop network structures

Bidirectional and dual bus wavelength division multiplexing (WDM) two-dimensional (2-D) multiple-plane optical interconnections with row-column multihop network structures using vertical-cavity surface-emitting lasers (VCSELs) and wavelength-selective detectors are analyzed and compared in terms of the expected number of hops (switching delay) and practical implementation considerations. The bidirectional WDM optical interconnection significantly reduces the necessary implementation hardware while maintaining the performance very closely compared to the dual bus architecture. Both WDM structures show significant performance improvements even when only three to five wavelengths are used. Also, the multihop efficiency is analyzed with the consideration of both electrical hops and optical hops.

Design and analysis of a scalable optical interconnection network for a computer cluster

This paper describes the dual-layer scalable optical intercon- nection network being developed at Tianjin University. The top layer of the network is a multiwavelength bidirectional optical bus, which has large bandwidth and low latency. The bus is made up of passive com- ponents. No wavelength-tunable devices are used. As a result, the bus has a low communication latency that is mainly determined by the optical fiber length. The sublayer of the network is a single-wavelength ring, which has low communication latency and high scalability. In each ring, a wavelength routing node is designed for data transmission between the ring and the optical bus. Each node computer is connected to the ring through an optical network interface card. The communication latency inside the ring is decreased by using synchronous pipelining transmis- sion. © 2001 Society of Photo-Optical Instrumentation Engineers.

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V/sub th/) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V/sub th/ MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V/sub th/ MOSFETs, which are cut off during standby. The high-V/sub th/, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words/spl times/16-bits SRAM test chip, which was fabricated with a 0.5-/spl mu/m multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 /spl mu/W, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads.

Plan: a high performance shared-media ATM LAN protocol

This paper presents the architecture and performance of a new shared media ATM LAN protocol known as pipelined-access local ATM network (PLAN) which has high performance and operates in native ATM mode for efficient and simpler interworking with backbone ATM networks. PLAN is a reservation type bidirectional broadcast bus system protocol in which overhead due to bus propagation delay is limited to a total of twice the end-to-end propagation delay per transmission frame irrespective of the number of stations on the bus. It is designed to (i) support multimedia traffic, (ii) dynamically allocate bandwidth to various types of traffic and provide fair media access to stations, (iii) provide throughput close to 100%, (iv) operate at high bit rates and (v) use packets of ATM cell size and format for interoperability with wide-area ATM networks. In this paper we present the architecture, analysis and performance of the proposed PLAN protocol under various multimedia traffic conditions. The results show that its throughput approaches 100%, is independent of traffic composition and increases slowly with bit rate. It decreases only slightly as the bus length and/or number of stations increase. The proposed PLAN protocol is seen to be well suited for high-speed multimedia ATM LAN and MAN applications in the ATM networking environment. © 1998 John Wiley & Sons, Ltd.

An Experimental Pattern Recognition System Using Bidirectional Optical Bus Lines

In the parallel processing system for matching input patterns with a vast number of reference patterns, bidirectional bus lines are required for data distribution and inter-unit communications. This paper describes an experimental pattern recognition system using bidirectional optical bus lines integrated using an Si LSI technique. A waveguide that can distribute an optical signal to all receiving branches from any transmission branch was designed, based on a finite-difference time-domain analysis. A complementary metal oxide semiconductor (CMOS) test chip for the pattern matching processing unit with amplifiers for a photodetector and drivers for a light emitting diode was also designed. This system selects the reference pattern most similar to an input pattern by using the waveguide. The basic operations of fabricated CMOS test chips were confirmed and the optical power branch ratios of the bidirectional optical waveguide were measured. In consideration of the measurement results, an improved optical waveguide for dividing optical power uniformly to branches is proposed.

Analysis of the operation of a bidirectional optical bus made of two semiconductor laser amplifiers running up to 1.555 Gb/s

We report an investigation of a bidirectional optical bus made of two semiconductor laser amplifiers (SLAs) that are used as modems. In addition to their amplification function, SLAs can also act as fast light modulators and detectors. They can hence be used as standard access components in an optical bus. Error-free transmission up to 1.555 Gb/s is achieved with −25-dBm optical power. © 1996 John Wiley & Sons, Inc.

Fan‐out intensity optimization of bidirectional photopolymer hologram‐based optical backplane bus

Fabrication of the bidirectional optical backplane bus, employing arrays of multiplexed polymer-based waveguide holograms on a waveguiding plate, is reviewed. An analysis of its functionality is presented for the first time. After an objective function for the system is established, the fan-out intensity fluctuations among all the different channels are minimized by solving a set of nonlinear equations numerically. To further ensure the validity of our calculation, a different objective function is considered and the same optimized result is obtained. Particularly, we optimized the fan-out distribution for the case in which nine boards on one side of the optical bus are presented. It was found that a globally optimized diffraction efficiency distribution exists and the minimum fan-out intensity after optimization is about 1.5% of the incident power, which means a minimum laser diode power for this bidirectional optical bus has to be above 7.0 mW for a system speed of 1.2 Gbit/s and a bit error rate of 10-15. Finally, the surface normal fanout beams come out of both directions of the backplane. Therefore, the best hardware implementation scheme integrates the processor/memory boards on both sides of the backplane bus. As a result, the optimal member of processor/memory boards is 16, i.e., 9 ± (922), rather than 9.

Bidirectional Active Bus and its Applications in Fiber Networks

Based on π couplers and optical amplifiers of two-way amplifications, we propose a Bidirectional Active Bus (BAB) structure for fiber networks which support two-way communications. The BAB structure at least saves half amount of bus fiber and optical amplifiers than the Dual Active Bus scheme [1, 2]. The structure applies to both single-optical-carrier and optical FDM/WDM fiber networks. In expanding/interconnecting fiber networks, the proposed BAB structure is free of Signal Circulation (SC) [3, 4] and Multipath Propagation (MP) [5] problems and independent of constellation of sub networks, and it uses less amount of fiber and optical filters than the MPL and SLB schemes [3, 4]. Star-BAB structure is suggested for large networks. The BAB structure has potential good survivability.

Bi-directional optical backplane bus for general purpose multi-processor board-to-board optoelectronic interconnects

We report for the first time a bidirectional optical backplane bus for a high performance system containing nine multi-chip module (MCM) boards, operating at 632.8 and 1300 nm. The backplane bus reported here employs arrays of multiplexed polymer-based waveguide holograms in conjunction with a waveguiding plate, within which 16 substrate guided waves for 72 (8/spl times/9) cascaded fanouts, are generated. Data transfer of 1.2 Gbt/s at 1.3-/spl mu/m wavelength is demonstrated for a single bus line with 72 cascaded fanouts. Packaging-related issues such as transceiver size and misalignment are embarked upon to provide a reliable system with a wide bandwidth coverage. Theoretical treatment to minimize intensity fluctuations among the nine modules in both directions is further presented and an optimum design rule is provided. The backplane bus demonstrated, is for general-purpose and therefore compatible with such IEEE standardized buses as VMEbus, Futurebus and FASTBUS, and can function as a backplane bus in existing computing environments.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Approximate analysis of a bidirectional looped dual‐bus network

AbstractThe characteristics of a system consisting of a number of terminals (queues) connected to two buses with slots in opposite directions are analyzed here. Cells arrive independently at each terminal and are sent to a gateway station on an empty slot. In addition, cells to be emptied at terminals may be loaded on the slots transmitted from the gateway station. Such a slot can be utilized by a destination terminal and its downstream terminals. A bidirectional bus structure is used to alleviate unfairness among terminals and to improve system reliability. A rigorous solution of a basic model consisting of only one queue is first obtained in analyzing this system. Next, an approximate analysis is performed on the target model utilizing the foregoing result. Since rigorous analysis of the characteristics of the target model is difficult, two approximate analyses are proposed here. the validity of these approximate analyses is evaluated by making comparisons with simulation results. the results indicate that the analyses presented in this paper are useful and are sufficiently accurate for the case without cell unloading.

Architecture and Performance of MLAN: A Multimedia Local ATM Network

In this paper we present a Multimedia Local ATM Network (MLAN) protocol suitable for campus environment which (i)operates in the native ATM mode, (ii)does dynamic and fair bandwidth allocation as per desired criteria, (iii)guarantees continuous access to real time and high priority data traffic, and (iv)offers connectionless as well as connection-oriented service for MLAN-ATM network communication. The protocol has been designed for a bidirectional broadcast bus system topology. A new 'polling inactive customers only (PICO)' reservation technique exploits the characteristics of the multimedia traffic which enabled us to reduce the average overhead due to bus propagation delay. Also, new concepts of secondary polling and transmissions have been introduced to improve LAN throughput under low traffic conditious. The protocol performance has been determined analytically as well as by computer simulation using a multimedia traffic model developed in the paper. Results show that the protocol performance remains the same at all traffic compositions if the offered load does not change and is independent of the bit rate (R) when R≥50 Mbps. Based on the results, the proposed broadcast bus system MLAN architecture is well suited for designing high speed multimedia ATM LANs with a modest number of terminals over a 1 to 3 km bus.

Space-time characteristics of ALOHA protocols in high-speed bidirectional bus networks

Studies the space-time characteristics of ALOHA multiple-access protocols in bidirectional bus networks where transmissions are in the form of packets of constant length. For point-to-point communications, the maximum throughput of unslotted ALOHA is known to be 1/(2e), independent of station configuration. The authors show that, with a uniform probabilistic station configuration, the maximum throughput of slotted ALOHA tends to a nonzero constant that is less than 1/(2e), when a, the end-to-end propagation delay normalized with respect to the packet transmission time, tends to infinity. However, when N stations are evenly spaced on the bus, the maximum throughput of slotted ALOHA vanishes as a tends to infinity. For broadcast communications, the maximum throughput of slotted ALOHA is well known to be 1.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Full CMOS video line-locked phase-locked loop system

A CMOS PLL (phase-locked loop) system for generation of a television line-locked clock in the frequency range 25 MHz to 40 MHz is described. The PLL system is designed for use as a generic building block with large-scale CMOS video signal processing integrated circuits. The development of a custom test chip version of the PLL system is reported. A test chip version of the PLL system has been fabricated in 0.8 mu m CMOS technology and tested to verify functionality and examine acquisition and racking behavior. The test chip version of the PLL includes a bidirectional test bus monitor system used to observe 28 signals and input five signals for the purpose of assessing circuit operation details. The open-loop measured noise bandwidth of the RC VCO (voltage-controlled oscillator) is -30 dB at 350 Hz. The short term stability within one second is approximately +or-150 Hz or 20 p.p.m., corresponding to 1.3 ns jitter in one horizontal line period of 63.5 mu s. >

General purpose valve amplifier with field bus interface

This paper presents a prototype of the next generation of valve ampilifier, which can control most proportional and servo valves plus some typical hydraulic servo systems with typical sensors. The amplifier consists of a 16-bit microcontroller, e 2- prom memory, various analog components and of a so-called ‘SmartPower’ chip, all on a single Europe 1-size printed circuit board. Its configuration and properties can be changed via its bi-directional serial bus, which can also be used to give commands and to ask for, e.g. diagnosis information.

A fault-tolerant air data/inertial reference system

The air data inertial reference system (ADIRS) described consists of a fault-tolerant air data inertial reference unit, a secondary air data attitude reference unit, and six air data modules. The ADIRS replaces the conventional inertial reference and air data systems and uses ARINC 629 bi-directional serial digital data bus interfaces. The ADIRS is designed to be the inertial and air data reference for the ARINC 651 integrated modular avionics (IMA) distributed architecture and provides low life cycle cost and high availability through high reliability, simple high integrity monitoring and deferred maintenance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Smart sensors

This paper is a state-of-the-art review of solid-state integrated and smart sensors. Smart sensors are defined as sensors that provide analog signal processing of signals recorded by sensors, digital representation of the analog signal, address and data transfer through a bidirectional digital bus and manipulation and computation of the sensor-derived data. In this paper the overall architecture and functions of circuit blocks necessary for smart sensors are presented and discussed. Circuit fabrication technologies are briefly discussed and CMOS technology is found to be ideally suited for many sensor applications. The challenges and techniques for the packaging of smart sensors are briefly reviewed and several specific examples of solid-state integrated and smart sensors are presented. It is believed that smart sensors will be needed in future closed-loop instrumentation and that control systems will be required in many application areas, including automative, health care, industrial processing and consumer electronics.