A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers

Abstract

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V/sub th/) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V/sub th/ MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V/sub th/ MOSFETs, which are cut off during standby. The high-V/sub th/, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words/spl times/16-bits SRAM test chip, which was fabricated with a 0.5-/spl mu/m multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 /spl mu/W, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads.