1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs

Abstract

Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-V/sub th/ nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words/spl times/16-bits SRAM test chip, fabricated with a 0.35-/spl mu/m MTCMOS/SIMOX process (shortened effective channel length of 0.17 /spl mu/m is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-/spl mu/W and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads.