Subthreshold leakage current reduction techniques for static random access memory

Abstract

The two main sources of power dissipation in CMOS circuits are dynamic and static power dissipation. Static power dissipation is due to leakage current when the transistor is normally off. The improvement in technology scaling has introduced very large subthreshold leakage current, therefore careful design techniques are very important in order to reduce subthreshold leakage current for low power design. Leakage current occurs in both active and standby modes. It is recommended to switch off the leakage current when the circuit is in standby mode, however it is not always possible to shut off the leakage current completely during this mode. Unlike gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low- V t transistors for its high-speed capability and High- V t transistors for very small leakage current. Multi-Threshold CMOS (MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Ideally the larger the threshold level the lower the leakage current, however, one must decide the optimum value of threshold level between the power switch (High- V t devices) and (Low- V t devices), as recovery delay tends to increase in higher threshold level. The full paper will discuss the design and performance of SRAM implemented using MTCMOS and VTCMOS biasing techniques. An improved sensing amplifier in the memory cell was incorporated to enhance the circuit performance.