Bias Temperature Stress Research Articles

Enhanced Stability Under Positive Bias Temperature Stress in Oxide Thin Film Transistors with Double Gate Structure By Improving Bottom Channel Interface

In this paper, we discuss the causes of reliability degradation in oxide TFTs with a double gate structure and propose methods for improvement. Reducing IGZO deposition power significantly improves PBTS (Positive Bias Temperature Stability) reliability in double gate structures. This improvement is attributed to reduction of excess oxygen defects accumulated at the bottom channel interface, as inferred from the difference in PBTS results for the top single gate and double gate structures

Quantitative Dynamic Evolution of Unoccupied States in Hydrogen Diffused InGaZnSnO TFT under Positive Bias Temperature Stress

Quantitative Dynamic Evolution of Unoccupied States in Hydrogen Diffused InGaZnSnO TFT under Positive Bias Temperature Stress

Heterogeneous monolithic 3D integration for hybrid vertical CMOS inverter using n-type IGTO TFT on p-type Si FET

In this work, a complementary metal oxide semiconductor (CMOS) vertical inverter using heterogeneous monolithic 3D (M3D) integration with p-type Si field-effect transistor (FET) and n-type indium-gallium-tin-oxide (IGTO) thin film transistor (TFT) was implemented and characterized. This CMOS inverter was attained by vertical stacking n-type IGTO TFT on p-type Si FET. Oxide semiconductor materials such as indium-gallium-zinc-oxide (IGZO), indium-tungsten-oxide (IWO), indium oxide (In2O3) and IGTO are being considered as potential options for channel materials in M3D integration technology due to high electrical characteristics and low temperature process. Among them, IGTO was employed as a channel material to achieve high mobility. We fabricated a n-type IGTO TFT using HfO2 and tungsten as a gate dielectric and electrode, respectively. The post-annealing process was conducted at 200–500 °C with 50 °C intervals. The IGTO TFT exhibits a high field-effect mobility (32.9 cm2/Vs), low sub-threshold swing (0.070 V/dec) and stable reliability behaviour (ΔVth < 0.4 V) against various external gate bias temperature stress tests in a low temperature (<500 °C). The stable heterogeneous vertical inverter performance such as voltage-transfer curve (VM = 1.66 V), voltage gain (30.1 V at VDD = 3 V), and noise margin (NMH = 1.22 V, NML = 1.34 V) were well behaved. This M3D integration-based hybrid CMOS inverter can be an alternative knob toward various device applications.

Plasma-enhanced atomic layer deposition of Sn-doped indium oxide semiconductor nano-films for thin-film transistors

Sn-doped indium oxide (ITO) semiconductor nano-films are fabricated by plasma-enhanced atomic layer deposition using trimethylindium (TMIn), tetrakis(dimethylamino)tin (TDMASn), and O2plasma as the sources of In, Sn and O, respectively. A shared temperature window of 150 °C- 200 °C is observed for the deposition of ITO nano-films. The introduction of Sn into indium oxide is found to increase the concentration of oxygen into the ITO films and inhibit crystallization. Furthermore, two oxidation states are observed for In and Sn, respectively. With the increment of interfaces of In-O/Sn-O in the ITO films, the relative percentage of In3+ions increases and that of Sn4+decreases, which is generated by interfacial competing reactions. By optimizing the channel component, the In0.77Sn0.23O1.11thin-film transistors (TFTs) demonstrate high performance, includingμFEof 52.7 cm2V-1s-1, and a highION/IOFFof ∼5 × 109. Moreover, the devices show excellent positive bias temperature stress stability at 3 MV cm-1and 85 °C, i.e. a minimalVthshift of 0.017 V after 4 ks stress. This work highlights the successful application of ITO semiconductor nano-films by ALD for TFTs.

Enhancing the Stability and Mobility of TFTs via Indium-Tungsten Oxide and Zinc Oxide Engineered Heterojunction Channels Annealed in Oxygen Ambient.

This study demonstrates a significant enhancement in the performance of thin-film transistors (TFTs) in terms of stability and mobility by combining indium-tungsten oxide (IWO) and zinc oxide (ZnO). IWO/ZnO heterojunction structures were fabricated with different channel thickness ratios and annealing environments. The IWO (5 nm)/ZnO (45 nm) TFT, annealed in O2 ambient, exhibited a high mobility of 26.28 cm2/V·s and a maximum drain current of 1.54 μA at a drain voltage of 10 V, outperforming the single-channel ZnO TFT, with values of 3.8 cm2/V·s and 28.08 nA. This mobility enhancement is attributed to the formation of potential wells at the IWO/ZnO junction, resulting in charge accumulation and improved percolation conduction. The engineered heterojunction channel demonstrated superior stability under positive and negative gate bias stresses compared to the single ZnO channel. The analysis of O 1s spectra showed OI, OII, and OIII peaks, confirming the theoretical mechanism. A bias temperature stress test revealed superior charge-trapping time characteristics at temperatures of 25, 55, and 85 °C compared with the single ZnO channel. The proposed IWO/ZnO heterojunction channel overcomes the limitations of the single ZnO channel and presents an attractive approach for developing TFT-based devices having excellent stability and enhanced mobility.

Charge Trapping and Emission during Bias Temperature Stressing of Schottky Gate GaN-on-Silicon HEMT Structures Targeting RF/mm Wave Power Amplifiers.

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed.

Temperature Dependent Anomalous Threshold Voltage Modulation of a-IGZO TFT by Incorporating Variant Gate Stresses

Amorphous indium gallium zinc oxide (a-IGZO) has recently made significant advancement as a key material for electronic component design owing to its compatibility with complementary metal oxide semiconductor technologies. A comprehensive analysis of reliability-related issues is required to determine the true potential of a-IGZO-based devices for next-generation electronics applications. To address this objective, we electrically characterize scaled-channel a-IGZO thin film transistors (TFTs) under positive bias (temperature) stress (PB(T)S). Both PBS and PBTS are characterized by positive and negative Vth shift, respectively, during the various gate stresses. In particular, the negative Vth shift is explained by the generation of donor-like traps stimulated by ionization of oxygen vacancy/hydrogen at elevated temperature. The TFTs exhibit relatively decent stability during the PBS operation. The analysis of devices with variant channel dimensions implies that long-channel devices exhibit relatively higher stability and performance compared to the short-channel ones. We also observe that the Vth can be controllably adjusted by employing the top gate (TG) with bottom gate sweep. Moreover, the stress-induced partial recovery mechanism is experimentally observed owing to detrapping of charges. Generally, the reported results infer a perceptive understanding of scaled-channel a-IGZO-TFTs which helps with shaping performance-enhancement strategies.

P‐2: Investigation of high mobility crystalline IGO TFT with top‐gate structure for LCD display application

The present paper reports the study of electrical characteristics and bias temperature stress (BT) stability of crystalline Indium‐Gallium oxide (IGO) dual‐gate thin film transistor (TFT) with top‐gate structure. TFT with normalized Ion over 100εA and PBTS/NBTIS of 0.35/‐2.85V was successfully fabricated. By adjusting oxygen partial pressure (O2%) and substrate temperature, we can control the wet etching rate (WER) of as‐deposited IGO film. After post annealing, crystalline IGO containing In2O3 phase with preferred orientation of (222) has been formed. The TFT characteristics uniformity and BT stability were found to depend on parameters of gate insulator (GI) deposition and pre‐treatment before GI. Based on experimental results, we propose high GI deposition temperature associated with low N2O plasma treatment power as the optimal condition for industrial production of crystalline IGO TFT.

80‐4: Highly Reliable, As‐Grown Crystalline InGaZnO TFTs by Spray Pyrolysis for Low‐Cost Manufacturing of High‐Resolution AMOLED Display

We report a low‐cost method for growing highly‐oriented crystalline InGaZnO (C‐IGZO) for a high‐resolution, active‐matrix thin‐film transistor (TFT) backplane for organic light‐emitting diode displays using spray pyrolysis. The self‐aligned, coplanar oxide TFT with an as‐grown C‐IGZO channel layer demonstrates a threshold voltage of‐0.35 V, saturation mobility of 33.99 cm2 V‐1 s‐1 , and subthreshold swing of 0.15 Vdec‐1, with an on/off current ratio exceeding 108 . Moreover, the C‐IGZO TFT with a channel length of 1.16 μm exhibits excellent operational stability under bias temperature stress.

14‐2: Development of High Mobility and Reliability Metal Oxide TFT for 13.2 inch AMOLED Display

The 13.2 inch AMOLED panel with 262 ppi has been fabricated with the high mobility metal oxide TFTs (thin film transistors). The high mobility oxide TFTs have high mobility ~34cm2 /Vs. On Gen. 6 glass, a small Vth variation with channel length 3.5um has been obtained. Moreover, the high mobility oxide TFT shows small Vth shift under positive/negative bias temperature stress (PBTS/NBTS).

P‐12: Improve the Reliability of a‐IGZO TFT through Optimizing the Threshold Voltage and Channel Thickness in AMOLED Hybrid Backplane

In the fabrication of flexible a‐IGZO and LTPS thin film transistor (TFT) hybrid backplane, various threshold voltage (Vth) of the a‐IGZO TFT was achieved in this paper by regulating the O2/Ar ratio during the deposition of a‐IGZO film by sputtering. The results show that the Vth increases with the increase of the O2/Ar ratio, and the reliability tests indicate that in a certain range negative adjustment of Vth can significantly improve the positive bias temperature instability (PBTI) of IGZO TFT, and maintain good electrical uniformity. The increase of the O2/Ar ratio reduces the number of oxygen vacancy (Vo) in the a‐IGZO channel, and thereby Vth is positively shifted, which is confirmed by the TCAD simulation. The Vth value can indicate the Vo concentration in a‐IGZO TFT channel partly, and appropriately higher amount of Vo is beneficial to improve the PBTI, which is attributed to Fermi level (EF) shifting closer to conduction band. Raised EF means less unoccupied trap states, resulting in less carrier trapping under PBTI. Furthermore, the research also explores different a‐IGZO channel thicknesses and finds that when the Vth values are similar, thinner channel layers endow a‐IGZO TFT with improved PBTI. By optimizing the Vth and channel thickness, a‐IGZO TFTs with a channel thickness of 25nm and a Vth value of 0.2V have been prepared in a hybrid backplane. Under positive bias temperature stress for 5 hours, the Vth is positively shifted less than 0.5 V, which could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.

P‐11: High Mobility BCE Oxide TFT Technology for Demux Driving Notebook LCD

Ln‐IZO based target was employed to deposit as a channel layer in amorphous Ln‐In‐Zn‐O thin‐film transistors. Here, we use the carrier/barrier bilayer stacked AOS TFTs to improve the mobility and stability. High mobility Ln‐oxide is for better charge transport. The barrier layer is fine‐tuned for better reliability. After optimization of the stacked structure of the active layer and the parameters of the PV SiO2 layer, the devices exhibited superior electric properties. The device shows high mobility (35.4 cm2/Vs) and small voltage shifts (1.1/‐1.5 V) of PBTS (positive bias temperature stress) and NBTIS (negative bias temperature illumination stress). We fabricated a 14 inch notebook liquid crystal display (LCD) with the Demux 1:3 circuit design using the high performance bilayer stacked TFTs.

P‐97: Improved Electrical Performance and Realiability of a‐IGZO TFT by N2O Plasma Treatment Optimization

This study investigates the abnormal reliability degradations observed under positive bias temperature stress (PBTS) in a‐IGZO TFTs treated by N2O plasma treatment and proposes a solution according to the presence of N2O plasma in the subsequent postprocess. In mass manufacture of a‐IGZO TFTs, N2O plasma is usually completely removed during the subsequent post‐plasma treatment processes. However, we maintained the presence of N2O plasma and analyzed its effect on device performance and reliability. While a‐IGZO TFTs fabricated with N2O plasmaremoved during the post‐process exhibited non‐ideal negative Vth shifts under PBTS, the devices fabricated with N2O plasma present during post‐processing showed superior electrical performance and reliability, avoiding the non‐ideal Vth shift phenomenon. This study shows that maintaining N2O plasma during the post‐process is an effective method for ensuring device reliability as well as improved performance of a‐IGZO TFTs in mass production.

P‐15: The Back‐channel Effect in Low Temperature Poly‐Si Thin Film Transistors

This paper addresses the mechanism of the back‐channel effect on TFTs (Thin Film Transistors) and proposes novel methods for characterizing and improving the stability of driving TFT devices, including back‐channel and back‐voltage testing. In comparison to routine sticking image and negative bias temperature stress testing, our methods aim to minimize the impact of intrinsic material fluctuations, allowing for independent measurement of the back‐channel effect on TFT device electrical characteristics. We also offer an enhanced option (N2 Plasma treatment of PI surface), that have been used for better the performance of products.

Facile routes to enhance doping efficiency using nanocomposite structures for high-mobility and stable PEALD-ITGO TFTs

In–Sn–Ga–O (ITGO) thin-film transistors (TFTs) fabricated by atomic layer deposition (ALD) are promising candidates for widespread semiconductor applications because of their high mobility and stability. To further improve the device characteristics, the doping efficiency of each cation must be increased. Here, we propose a facile method to enhance the device characteristics using plasma-enhanced ALD-nanocomposite (NC) structures. The deposition of SnO2 materials within the In2O3 layer of the ITGO film with the NC-ITO structure accelerates the reduction of In2O3 (In0: 35.3 % →46.1 %), thereby stabilizing SnO2 (Sn4+: 71.0 % →89.1 %). In addition, this process significantly decreases the fraction of oxygen-related defects (Odefect: 24.0 % →17.6 %) because Sn–O has a substantially higher bond dissociation energy than In–O. Consequently, the ITGO TFT with the NC-ITO active layer exhibits considerable improvements in the electrical parameters, such as an increase in the field-effect mobility from 41.9 to 54.5 cm2/V s and an enhancement in the subthreshold swing from 69.8 to 64.8 mV/decade. In addition, the device shows excellent results for negative bias illumination stress and positive bias temperature stress, with the differences in the threshold voltage shift being −0.22 and + 0.06 V, respectively.

Enhancement in electrical properties of dual-active-layer amorphous SiZnSnO/SiInZnO thin film transistors

Bi-layer thin film transistors (TFTs) have been fabricated with a channel structure comprising a dielectric layer, a semiconducting amorphous-Si-In-Zn-O (a-SIZO) layer, and a semiconducting amorphous-Si-Zn-Sn-O (a-SZTO) layer, aiming to improve field effect mobility and stability. These films were deposited using RF sputtering at room temperature. The TFTs with a bottom gate top contact, processed at 500 °C, exhibited high mobilities (>32 cm2 V−1 s−1) along with a current on/off ratio of approximately 108 and a subthreshold swing (SS) value below 0.5 V decade−1 primarily because of reduced trap density and presence of highly conducting ultrathin a-SIZO layer. Furthermore, the bi-layer TFTs demonstrated notable stability under negative and positive bias temperature stress conditions.

Compositionally engineered amorphous InZnO thin-film transistor with high mobility and stability via atmospheric pressure spatial atomic layer deposition

Amorphous indium-zinc oxide (IZO) thin films, featuring indium atomic concentrations between 35.2 and 64.2 at.%, were fabricated using atmospheric pressure spatial atomic layer deposition (AP S-ALD) at 250 °C, employing trimethylindium (TMI) and diethylzinc (DEZ) as precursors and ozone as the reactant, based on the atomic layer processing. The crystallinity and chemical bonding states of the IZO films were found to vary with the metal cation composition, as confirmed by X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS). We fabricated thin-film transistors (TFTs) employing the IZO films as the active layer on polyimide (PI) substrates, achieving high mobility (45.7 cm2/V·s), excellent bias-temperature stress (BTS) stability (ΔVTH = 0.63 V), and maintaining stable electrical properties even after mechanical bending tests along two different axes. This study highlights the successful development of high-performance flexible devices by precisely controlling the metal cation composition using AP S-ALD based on high deposition rate.

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress.

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

P‐1.9: Enhanced Stability Under Positive Bias Temperature Stress of Ln‐Doped InZnO Thin Film Transistors Fabricated with Back‐channel‐etch Structure

P‐1.9: Enhanced Stability Under Positive Bias Temperature Stress of Ln‐Doped InZnO Thin Film Transistors Fabricated with Back‐channel‐etch Structure