Bias Temperature Stress Research Articles

A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film

This work studies and presents an inner-interface trapping physical model for the ultra-thin (effective oxide thickness=15 Å) zirconium oxide (ZrO2) film to explain its hysteresis phenomenon. The shift of the capacitance–voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination (∼45 mV). The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance–voltage characteristics and the different turn-around voltages of the current density–voltage characteristics of the zirconium dielectrics.

Mobile Ion Detection in Organosiloxane Polymer Using Triangular Voltage Sweep

The triangular voltage sweep (TVS) technique has been traditionally used for mobile ion detection in gate oxides. In this paper, we present and discuss the results of TVS measurements on plasma enhanced chemical vapor deposited (PECVD) silicon oxide and a low dielectric constant hybrid organosiloxane polymer (HOSP). A variety of gate metals were studied to detect and separate mobile ion effects associated with the metal. For the PECVD oxide, no peak was detected with Al gate metal, whereas a large peak was detected with Cu; allowing us to correlate the observed peak to mobile copper ions. TVS traces revealed no peak for Pt/HOSP capacitors, but peaks were detected with Cu, Ta, and Al capacitors. Thus, the appearance of mobile ion peaks in the TVS traces correlated well with the previously published bias-temperature stressing (BTS) induced instability of these capacitors, where the flatband voltage shifts during BTS were in the order with no shift observed for Pt capacitors. The effects of temperature, voltage sweep rate, and bias hold time were also investigated for Al/HOSP and Cu/HOSP capacitors. Cu peaks were one to two orders of magnitude smaller than Al peaks under all conditions investigated. It was concluded that the peaks originate from the gate metal. © 2002 The Electrochemical Society. All rights reserved.

Copper drift in methyl-doped silicon oxide film

Drift of copper (Cu) ions into methyl-doped silicon oxide film, a promising low-dielectric-constant (low-κ) material for inter-layer dielectrics applications in ultralarge scale integrated circuit (ULSI) interconnects, was investigated using bias temperature stressing (BTS)/capacitance–voltage (C–V), current–voltage (I–V) at elevated temperatures and time-dependent dielectrics breakdown (TDDB) tests. Standard and control metal–insulator–semiconductor capacitor test samples with “sandwich” dielectric layer structures were used in the tests. BTS in nitrogen (N2) ambient at an electric field magnitude up to 1.5 MV/cm and with temperatures between 175 and 275 °C was used to accelerate the Cu ion drift. By studying flat band voltage shift in C–V tests, leakage current magnitude in I–V tests and time to fail in TDDB tests, it is demonstrated that Cu ions readily drift into methyl-doped silicon oxide under electric fields at elevated temperatures. Results obtained using different techniques correlate well to each other. The activation energy of Cu drift is determined to be 0.76 eV in N2 ambient. The film is found to have poorer resistance to Cu drift than silicon oxide (SiO2) deposited using plasma-enhanced chemical vapor deposition (PECVD). Therefore, good Cu drift barrier layers are required for reliable ULSI interconnects using this low-κ material. A thin layer of PECVD SiC is proven to be a good Cu drift barrier layer.

Plasma surface modification for ion penetration barrier in organosiloxane polymer

Low dielectric constant (low-κ) hybrid organosiloxane polymer (HOSP) displayed larger instability with Al compared to Cu capacitors when investigated using the bias temperature stressing (BTS) and triangular voltage sweep (TVS) techniques. We attributed this instability to ion penetration from the gate metal. As SiO2 is a well-known barrier against Al penetration, an attempt was made to create a SiO2-like surface on HOSP using different plasma treatments. The plasma conditions were selected to minimize bulk damage to the polymer. While N2O and O2 plasmas caused bulk electrical damage, N2 and Ar plasma treatments dramatically reduced ion penetration from the Al gate into HOSP. This was seen from the decrease in the BTS C–V shift as well as the TVS ion peak area. A short (1 min) low-power (30 W) N2 plasma treatment was effective as an aluminum ion penetration barrier, without significantly increasing the refractive index or dielectric constant value of HOSP. Formation of a SiO2-like surface was confirmed from x-ray photoelectron spectroscopy investigations. The above plasma-treatment approach reveals one possible route to attain the “zero barrier thickness” requirement for interconnect systems.

Negative bias temperature stress on low voltage p-channel DMOS transistors and the role of nitrogen

Negative bias temperature stress on low voltage p-channel DMOS transistors and the role of nitrogen

Interactions Between Nanoporous Silica and Copper

Porous materials have been proposed to replace as the interlayer dielectric in future microelectronic devices. The interaction of porous materials with contiguous layers is very important for the long-term stability of devices. To investigate the interaction of silica xerogels with Cu, thin Cu layers were deposited on xerogel films and subsequently annealed. When Cu films were directly exposed to an oxidizing environment, they underwent morphological changes, and these changes may lead to the erroneous interpretation of the Rutherford backscattering spectra as depicting metal diffusion. When the samples are capped with an layer, which precludes oxidation, Cu does not show diffusion into the xerogel when annealed up to 650°C. Bias-temperature stressing (BTS) was conducted to assess Cu drift through the xerogel in the presence of an electric field. Contrary to what is normally observed with other dielectrics, the leakage current and capacitance-voltage (C-V) curve shifts were larger with an Al electrode than with a Cu electrode. When the organic capping groups are removed from the xerogel by high temperature annealing before metal deposition, C-V tests indicate Cu ion diffusion occurs even as low as 100°C. Surface modification of the xerogel by trimethylsilyl groups may contribute to the smaller charge injection from the Cu/xerogel interface or to the inhibition of Cu diffusion, thus offering the possibility of designing future monolayer diffusion barriers for porous materials. A model of diffusion through porous solids has been developed. Two possible paths of mass transfer in porous solids are identified: bulk and surface. Three driving forces are also considered: concentration gradient, electric field, and curvature gradient. The upper limit of Cu diffusivity in xerogel was estimated, and the model simulated the current observed during BTS testing reasonably well. © 2002 The Electrochemical Society. All rights reserved.

Barrier integrity testing of Ta using triangular voltage sweep and a novel CV-BTS test structure

Numerous techniques are available for evaluating the efficacy of barrier materials at preventing the diffusion of copper into dielectric materials. In this study, the capability of triangular voltage sweep (TVS) as a means of determining barrier integrity is investigated. Also in the study, a new test structure is introduced for performing capacitance voltage bias temperature stress (CV-BTS) tests. This test structure, which is designed to mimic barrier performance at the bottom of vias where step coverage is a challenge, was used to determine the diffusion barrier properties of PVD deposited tantalum as a function of Ta thickness in 0.25-μm vias.

Conduction-related voltage instabilities in double-layer dielectric films

Threshold voltage shift induced on parasitic metal–insulator–semiconductor field-effect transistors by bias-temperature stress in the presence of double-layer insulating stacks is studied as a function of the stack composition and measurement conditions. It is shown that the threshold-voltage shift (ΔVT) closely depends on the conductance difference between the two insulating layers. This shift is completely reversible being larger if the conductance difference is higher and more charge is injected into the dielectric stack. In the case of Si3N4/SiO2 insulating stacks, it is further demonstrated that the voltage shift is caused by charges transferred via the nitride and accumulated in the nitride and/or at the nitride/oxide interface. A first-order charge transfer model presented here explains the observed voltage shift.

Enhanced Negative-Bias-Temperature Instability of P-Channel Metal-Oxide-Semiconductor Transistors due to Plasma Charging Damage

The effects of plasma charging on the negative-bias-temperature instability (NBTI) of p-channel metal-oxide-semiconductor (PMOS) transistors were explored in this work. It is clearly shown that the threshold voltage shift during bias-temperature stressing (BTS) could be enhanced by plasma charging damage. More importantly, we also found that electron trappings are aggravated by plasma charging, even on new devices with large antenna area ratios prior to BTS. Our charge pumping current measurements confirm that the interface-state density is increased for devices with large antennas, both before and after the BTS. This indicates, without ambiguity, that electron trapping is solely responsible for the observed low (in absolute value) threshold voltage in new devices with large antennas. Finally, it is proposed that the NBTI characterization can be used as a sensitive method for characterizing the antenna effects in devices with ultrathin gate oxide, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down.

Noncontact Measurement of Sodium Ions in Silicon Oxide

In this study, we discuss the evaluation of sodium ions in silicon oxides (SiO2) by noncontact capacitance–voltage measurement and ultraviolet (UV) irradiation. The oxide charge (Nox) of sodium-contaminated wafer decreases with UV irradiation. The dependence of Nox on the UV wavelength indicates that the electrons excited by UV light are injected from the silicon into the oxide conduction band and subsequently trapped in the SiO2. The injected electrons are trapped only in the vicinity of the SiO2 surface, resulting in the neutralization of the sodium ions located near the surface when a wafer is irradiated by UV light at room temperature. The UV irradiation at elevated temperature, however, enables the sodium ions to move from the Si/SiO2 interface toward the SiO2 surface and to be completely neutralized. The change in Nox with UV irradiation shows good agreement with the sodium ion concentration determined by the bias temperature stress method.

The Simulation of Copper Drift in SiO2 during Bias Temperature Stress (BTS) Test

AbstractIn order to develop a reliable interconnect integration scheme by using Cu in ultra large scale integrated devices (ULSI), the evolutions of the concentration profile of copper ions in SiO2 was simulated under bias temperature stress (BTS) test. Diffusion equation was solved numerically in two electric field modes. One is constant electric field mode where copper drift was simulated with the assumption that electric field is constant within SiO2 film. In variable electric field mode, simulation was carried out considering the variation of electric field in SiO2 due to copper ions. The diffusion of copper ions in variable electric field mode is slower than that in constant electric field mode, because copper ions in SiO2 reduce electric field near the interface between Cu and SiO2. Flatband voltage shift ) (ΔVFB increases parabolically as BTS time increases in constant electric field mode. However, it has linear relation with BTS time in variable electric field mode, which is typically observed in experiments.

Highly reliable uni-travelling-carrier photodiodes for 40 Gbit∕s optical transmission systems

The reliability of InP/InGaAs uni-travelling-carrier photodiodes has been studied. A failure rate of 42 FIT at 25/spl deg/C was estimated from long-term bias-temperature stress tests. Stable operations for over 2000 h were also confirmed under higher-power optical input conditions.

Surface-Processing-Enhanced Copper Diffusion into Fluorosilicate Glass

This study investigated copper diffusion into processed fluorosilicate glass (FSG). It is observed that the surface process enhances the flatband voltage shift of the Cu/FSG/Si capacitor structure under bias-temperature stress. Secondary-ion mass spectroscopy analysis confirmed that the flatband voltage shift was due to Cu diffusion into the FSG film. Thermal desorption spectrometer analysis indicated that the surface damage layer took up more moisture. A surface-damage-layer-enhanced Cu ionization model was then proposed to explain the observation. The investigation concludes that the diffusion of Cu into FSG is strongly dependent on the surface condition of the FSG film. The proposed model also provides explanation for the inconsistent results reported in previous literature. © 2001 The Electrochemical Society. All rights reserved.

Metal drift behavior in low dielectric constant organosiloxane polymer

Metal drift into a low dielectric constant (low κ) hybrid organosiloxane (OS) polymer has been investigated using metal/OS/SiO2/Si capacitors. Compared to Cu, Al gate metal capacitors showed larger flatband voltage shifts in the capacitance–voltage (C–V) curves upon bias temperature stressing (BTS). To elucidate the mechanism and source of this bias instability, further BTS experiments were performed with gate metals tantalum and platinum. It is suggested that all these metals, except Pt, drift into the dielectric and the extent of drift appears to be directly related to the metal’s tendency to oxidize. The calculations, assuming singly ionized metal species, show that the charges/cm2 entering the dielectric fall in the order Pt<Cu<Ta<Al. A mechanism is proposed linking the presence of oxygen in OS to the ionization of the metals, and consequent drift through the dielectric under applied electric fields.

Dielectric and Barrier Properties of Spin-On Organic Aromatic Low Dielectric Constant Polymers FLARE and SiLK

This work investigates the dielectric and barrier properties of two species of organic aromatic low dielectric constant (low-k) polymers, namely, FLARE and SiLK. Experimental results indicate that both of the low-k polymers exhibit acceptable thermal stability with respect to a thermal annealing at 400°C for 8 h in an ambient. Moreover, they show a good dielectric barrier property against Cu penetration under bias-temperature stressing (BTS) at 150°C with an applied effective field of 0.8 MV/cm. Nevertheless, an anomalous instability of the capacitance-voltage curve was observed for the first time under BTS. This finding is explained by the proposed model of stress induced dielectric polarization charges within these organic aromatic polymers. The polarization instability may seriously degrade the long term reliability of circuit operations. © 2001 The Electrochemical Society. All rights reserved.

Junction leakage current degradation under the off-state bias-temperature stress: a new reliability assessment method for high-density DRAMs

A new reliability assessment method on retention time failure for high-density DRAMs under off-state bias-temperature (B-T) stress was suggested and investigated using the well-known gated-diode test pattern. The transistor junction leakage current degradation, total junction leakage current especially including gate-induced drain leakage (GIDL) component, under the off-state B-T stress was found to be more sensitive than widely-used gate-oxide degradation under the Fowler-Nordheim (F-N) tunneling stress. The off-state bias stress also gives significantly higher degradation on the gate-oxide stress-induced leakage current (SILC) than F-N tunneling current stress. The features of the off-state B-T stress which gives stress to almost all transistor leakage components and the mechanism of the junction leakage current degradation under the off-state bias condition were discussed.

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.

Key reliability issues for copper integration in damascene architecture

Electromigration and the effects of Cu concentration in intra-metal dielectrics have been examined: these two key reliability issues are fundamental in the development of Cu based interconnects. Several experiments have been performed to highlight the sensitivity of the electromigration performances with respect to the various process variants: the impact of annealing, of dielectric capping SiN deposition process and the role of the environment on the diffusion mechanisms have been studied. Furthermore, the dependence of the line-width on the current and temperature induced transport mechanisms have been analyzed. Once more, process variations have been demonstrated to influence strongly the final behavior of Cu interconnects in dual-damascene architecture. Intra-metal dielectric reliability has also to be considered as a potential reliability issue and bias-temperature stress tests have proven that if the amount of Cu left behind the barrier during the process is not precisely controlled, the role of the barrier as a diffusion inhibitor could be questionable.

Evolution of the Cu-Al Alloy/ SiO2 Interfaces during Bias Temperature Stressing

Alloys of copper with small amounts of aluminum have recently been investigated as the interconnect metal directly on or as the low resistivity diffusion barrier/adhesion promoter between copper and In the present work the electrical stability of the metal-oxide-semiconductor (MOS) capacitors of such alloys on thermal oxide on p-silicon was investigated. MOS samples preannealed at 250°C and subjected to bias temperature stressing (BTS) at 200 and 250°C under an electrical field of 1.5 or 2 MV/cm showed stable C-V behavior with no observed shifts along the voltage axis. However, an observed decrease in the by about 4-5% was associated with the higher BTS temperature or the field. Such changes were not observed if the preanneal was performed at 300°C instead of 250°C. Our X-ray photoelectron spectroscopy (XPS) analyses of the metal/ interface suggest that the observed instabilities in samples preannealed at 250°C (not observed in those preannealed at 300°C) are related to the interface interactions between Al (in the alloy) and The higher temperature preanneal or higher BTS conditions led to stabilization of this interface leading to stable MOS behavior as is also supported by the results of the measurements which is also presented and discussed in this work. © 2001 The Electrochemical Society. All rights reserved.

Characteristics of Large-Area Plasma Enhanced Chemical Vapor Deposited TEOS Oxide with Various Short-Time Plasma Treatments

AbstractIn this work, high quality silicon dioxide (SiO2) films were prepared by large-area plasmaenhanced chemical vapor deposition (LA-PECVD) using tetraethylorthosilicate(TEOS)-oxygen based chemistry. The effects of various short-time plasma treatments on these as-deposited TEOS oxide were also investigated. Different plasma treatments such as O2, N2O, and NH3 were used in our experiments. Electrical characteristics were exploited to examine the effects of plasma treatments. It was shown that after N2O, and NH3 plasma treatments, the electrical strength of oxide was enhanced. Besides, NH3 plasma treatment exhibited the highest enhancement efficiency. O2- plasma treatment, however, showed some harmful effects on the electrical properties of the TEOS oxide. The reliability tests including charge to breakdown (Qbd) and bias temperature stress (BTS) were also analyzed in these samples. Although better pre-stress characteristics were observed in those samples treated by NH3-plasma, samples with N2O plasma treatment showed superior stress endurance. Consequently, N2O plasma treatment seems to be the best candidate for future TFTs under the consideration of long-term reliability.