Bias Stress Stability Research Articles

Strain-dependent charge trapping and its impact on the operational stability of polymer field-effect transistors

Despite recent dramatic improvements in the electronic characteristics of stretchable organic field-effect transistors (FETs), their low operational stability remains a bottleneck for their use in practical applications. Here, the operational stability, especially the bias-stress stability, of semiconducting polymer-based FETs under various tensile strains is investigated. Analyses on the structure of stretched semiconducting polymer films and spectroscopic quantification of trapped charges within them reveal the major cause of the strain-dependent bias-stress instability of the FETs. Devices with larger strains exhibit lower stability than those with smaller strains because of the increased water content, which is accompanied by the formation of cracks and nanoscale cavities in the semiconducting polymer film as results of the applied strain. The strain-dependence of bias-stress stability of stretchable OFETs can be eliminated by passivating the devices to avoid penetration of water molecules. This work provides new insights for the development of bias-stable stretchable OFETs.

Carrier modulation and effective passivation of tin oxide thin-film transistors by organic surface doping

Doping is a useful technique for metal oxide thin-film transistors (TFTs) to adjust the threshold voltage and charge carrier density. However, a notable drawback is the disruption of the microstructure caused by doping crystalline lattice, leading to a partial decrease in charge carrier mobility. In this work, we suggest a surface doping technique that modifies the carrier concentration and passivates the device surface while preserving the channel layer lattice structure through the use of organic dopant molecules. It is shown that tin oxide (SnO2) TFTs doped in this manner typically exhibit improved electrical characteristics, particularly greater mobility and a noticeably lower threshold voltage, without negatively affecting the devices on/off current ratio. Furthermore, compared to pristine devices, bias stress stability and long-term durability are also enhanced. These findings suggest that surface doping may find use in high-performance oxide semiconductor devices and circuits.

Viable Approach of Tuning Oxide Semiconductor Thin Films in Solution‐Processed Heterojunction Thin Films Transistors for Both Higher Performances and Stability

AbstractMetal‐oxide thin‐film transistors (TFTs) have garnered much attention because of their advantages such as high transparency, low leakage current, and low processing temperature. However, there is a need to continuously improve their mobility and bias stability for application to next‐generation advanced electronics. In this study, the thickness of bilayer semiconductors is finely controlled to enhance the charge transport characteristics and bias stability in solution‐processed heterojunction oxide TFTs. The thicknesses of the top and bottom layers in the bilayer are individually adjusted by controlling solution molarity. The introduction of a bilayer channel improved the electrical performance of oxide TFTs via effective charge transport. However, trap‐limited conduction becomes dominant in the bilayer with an excessively thick top layer, thereby leading to a significant reduction in mobility and positive bias stability. Meanwhile, although increasing the bottom layer thickness contributes to improved mobility and reliability, it causes a serious negative shift in threshold voltage (VTH). TFTs with an optimized bilayer structure show high mobility at a VTH close to 0 V and have particularly excellent positive bias stress stability. This study on bilayer channel thickness will be beneficial for developing advanced transistors with optimized bilayer or multilayer channels.

Hypoeutectic Liquid Metal Printing of 2D Indium Gallium Oxide Transistors.

2D native surface oxides formed on low melting temperature metals such as indium and gallium offer unique opportunities for fabricating high-performance flexible electronics and optoelectronics based on a new class of liquid metal printing (LMP). An inherent property of these Cabrera-Mott 2D oxides is their suboxide nature (e.g., In2O3-x), which leads high mobility LMP semiconductors to exhibit high electron concentrations (ne >1019cm-3) limiting electrostatic control. Binary alloying of the molten precursor can produce doped, ternary metal oxides such as In-X-O with enhanced electronic performance and greater bias-stress stability, though this approach demands a deeper understanding of the native oxides of alloys. This work presents an approach for hypoeutectic rapid LMP of crystalline InGaOx (IGO) at ultralow process temperatures (180°C) beyond the state of the art to fabricate transistors with 10X steeper subthreshold slope and high mobility (≈18cm2Vs-1). Detailed characterization of IGO crystallinity, composition, and morphology, as well as measurements of its electronic density of states (DOS), show the impact of Ga-doping and reveal the limits of doping induced amorphization from hypoeutectic precursors. The ultralow process temperatures and compatibility with high-k Al2O3 dielectrics shown here indicate potential for 2D IGO to drive low-power flexible transparent electronics.

Enlightenment of Deionized‐Water Bathing IGZO TFTs

AbstractAt present, amorphous indium–gallium–zinc oxide (IGZO) semiconductor has become the most commonly used semiconductor material and is widely used in flat panel displays and various sensors, but its performance is greatly affected by environmental factors, especially water. This study investigates the instability of IGZO thin‐film transistors (TFTs) soaked in deionized water. After 24 h bathing, the field‐effect mobility and threshold voltage change a little, but the subthreshold swing, positive bias stress and negative bias stress stability undergo clear degradation. Through comprehensive examination of the changes in the chemical composition, surface morphology and thickness of the IGZO films, it's found that IGZO experiences selective etching by deionized water, and consequently the film surface becomes rough and rich of In and oxygen vacancies, which can explain the variations on device performance well. In addition to the bathing experiment performed on In2O3, Ga2O3, and ZnO TFTs, a schematic image of the reaction between water and IGZO is depicted, showing the preferential loss of Ga and Zn located next to the oxygen vacancy.

Thermal Dehydrogenation Impact on Positive Bias Stability of Amorphous InSnZnO Thin-Film Transistors.

Recently, the growing demand for amorphous oxide semiconductor thin-film transistors (AOS TFTs) with high mobility and good stability to implement ultrahigh-resolution displays has made tracking the role of hydrogen in oxide semiconductor films increasingly important. Hydrogen is an essential element that contributes significantly to the field effect mobility and bias stability characteristics of AOS TFTs. However, because hydrogen is the lightest atom and has high reactivity to metal and oxide materials, elucidating its impact on AOS thin films has been challenging. Therefore, in this study, we propose controlling the hydrogen quantities in amorphous InSnZnO (a-ITZO) thin films through thermal dehydrogenation to precisely reveal the hydrogen influences on the electrical characteristics of a-ITZO TFTs. The as-deposited device containing 15.69 × 1015 atoms/cm2 of hydrogen exhibited a relatively low saturation mobility of 18.1 cm2/V·s and poor positive bias stress stability. However, depending on the extent of thermal dehydrogenation, not only did the hydrogen quantity and interface defect density (DIT) decrease but also the conductivity and surface energy increased due to the rise in oxygen vacancies and hydroxyl groups in a-ITZO thin films. As a result, the a-ITZO TFT with a hydrogen amount of 4.828 × 1015 atoms/cm2 showed that the saturation mobility improved up to 36.8 cm2/V·s, and positive bias stress stability was remarkably enhanced. Hence, we report the ability to manage the hydrogen quantity with thermal dehydrogenation and demonstrate that high-performance a-ITZO TFTs can be realized when an appropriate hydrogen concentration is achieved.

Mobility and current boosting of In-Ga-Zn-O thin-film transistors with metal capping layer oxidation

This study investigates the effect of an oxidized Ta capping layer on the boosting of field-effect mobility (μ FE) of amorphous In-Ga-Zn-O (a-IGZO) Thin-film transistors (TFTs). The oxidation of Ta creates additional oxygen vacancies on the a–IGZO channel surface, leading to increased carrier density. We investigate the effect of increasing Ta coverage on threshold voltage (V th), on-state current, μ FE and gate bias stress stability of a-IGZO TFTs. A significant increase in μ FE of over 8 fold, from 16 cm2 Vs−1 to 140 cm2 Vs−1, was demonstrated with the Ta capping layer covering 90% of the channel surface. By partial leaving the a-IGZO uncovered at the contact region, a potential barrier region was created, maintaining the low off-state current and keeping the threshold voltage near 0 V, while the capped region operated as a carrier-boosted region, enhancing channel conduction. The results reported in this study present a novel methodology for realizing high-performance oxide semiconductor devices. The demonstrated approach holds promise for a wide range of next-generation device applications, offering new avenues for advancement in metal oxide semiconductor TFTs.

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway.

Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures offer promising alternative materials for next-generation high-density memory devices. The complex vertical stacking process of memory devices significantly increases the probability of encountering internal contact issues. Conventional surface treatment methods developed for planar devices necessitate efficient approaches to eliminate contact issues at deep internal interfaces in the nanoscale complex structures of AOS devices. In this work, we report the pioneering use of palladium thin film as a high-efficiency active hydrogen transfer pathway from the outside to the internal contact interface via low-temperature postannealing in the H2 atmosphere, and the formation of highly conductive metallic interlayer effectively solves the contact issues at the deeply buried interfaces in devices. The application of this method reduced the contact resistance of Pd electrodes/amorphous indium-gallium-zinc oxide (a-IGZO) thin-film by 2 orders of magnitude, and thereby the mobility of thin-film transistor was increased from 3.2 cm2 V-1 s-1 to nearly 20 cm2 V-1 s-1, preserving an excellent bias stress stability. This technology has wide applicability for the solution of contact resistance issues in oxide semiconductor devices with complex architectures.

Negative bias stress stable PtOx/InGaZnOx Schottky barrier diodes optimized by oxygen annealing

In this work, bottom-Schottky-structure InGaZnOx (IGZO) Schottky barrier diodes (SBDs) with sputtered PtOx anodes were fabricated and annealed in oxygen at different temperatures. Critical parameters and negative bias stress (NBS) stability of SBDs with different annealing temperatures are investigated. With the annealing temperature increases, the barrier height and rectification ratio of the SBDs exhibited a rising-then-declining trend, while the ideality factor slightly increased until 200 °C. The SBDs show up overall reliability except for a leakage current rising trend under light, which can be attributed to free electron generation from the ionized oxygen vacancy. Among all the SBDs, the 175 °C annealed ones exhibited the best overall performance, including a high barrier height of 0.89 eV, an ideality factor of 1.14, and a large rectification ratio of over 108. Compared to the initial SBDs, the annealed ones showed up great improvement in NBS stability except for the 200 °C annealed ones, which was permanently degraded and not able to recover to original states. According to experimental result analysis and IGZO material characteristics, a stability model based on the subgap trap transition from VO2+ to VO and new VO2+ creation was proposed, which applies to both the short-term and long-term NBS tests. The results above demonstrate that oxygen annealing at appropriate temperature is an effective method to improve both device performance and NBS stability for PtOx–IGZO SBDs.

Cation doping strategy for improved carrier mobility and stability in metal-oxide Heterojunction thin-film transistors

The heterojunction channel architecture has emerged as a viable solution to enhance the performance of metal-oxide thin-film transistors (TFTs), addressing the performance limitations of single-channel counterparts. However, carrier mobility enhancement through a channel thickness design often encounters significant challenges such as the negative threshold voltage (Vth) shift. In this study, we present a cation doping strategy, designed to regulate Vth shift while simultaneously boosting carrier mobility in zinc-tin-oxide (ZTO)-based heterojunction TFTs. A comprehensive investigation of ZTO-based semiconductors was conducted to explore the impact of cation doping on the energy band structure and to find an optimal heterojunction channel structure for high carrier mobility and stability. The resulting ZTO/Ti-doped ZTO (Ti:ZTO) heterojunction TFTs demonstrated a field-effect mobility of 39.7 cm2/Vs, surpassing the performance of ZTO TFTs (16.1 cm2/Vs), with a minimal change in the Vth. Furthermore, the ZTO/Ti:ZTO TFTs exhibited enhanced bias-stress stability compared to the ZTO TFTs. We attribute the improved mobility and stability to the electron accumulation near the oxide channel heterointerface facilitated by band bending and defect passivation effect arising from the Ti:ZTO back-channel layer, respectively.

Bias stress stabilities of PMMA-passivated indium-gallium-zinc-oxide thin-film transistors after 100 °C steam exposure

Bias stress stabilities of the polymethyl methacrylate (PMMA)-passivated IGZO thin-film transistors (TFTs) after being exposed in a normal and harsh (100 °C steam) environment were studied, in order to comprehensively evaluate protection effects of PMMA. In a normal environment, the PMMA-passivated TFTs exhibited normal switching characteristics and electrical stabilities. However, the switching characteristics and bias stress stabilities were changed after being exposed on 100 °C steam. There were negative Vth shifts on the transfer curves of the steam-exposed IGZO TFTs. Our XPS analysis revealed that the negative ΔVth was related to the steam-induced H2O molecules throughout the IGZO films, which acted as electron donors to introduce more electrons in the front channel. Under PBS, the steam-exposed IGZO TFTs showed an abnormal negative Vth shift while the un-exposed IGZO TFTs showed negligible Vth shift. This abnormality was ascribed to the electrons released from steam-induced H2O molecules, which render the conductive path more easily opened. Under NBS, the steam-exposed IGZO TFT presented larger negative Vth shift than the un-exposed TFT. This result was interpreted in terms of the steam-induced donor states (H2O molecules) near or at channel/insulator interface. Under PBTS and NBTS, the changes in Vth for steam-exposed TFTs were similar to those for un-exposed TFTs. Such a similarity indicates that steam exposure had no effects on NBTS and PBTS stabilities. It was understood in terms that the steam-induced H2O+ recombined with the electrons released from the steam-induced H2O molecules under bias stress, forming H2O to compensate the thermally-induced H2O adsorption. Our results suggest that one-micron-thick PMMA passivation layer enabled to protect IGZO TFTs from H2O in a normal environment, but it provided inadequate protection in a harsh environment. Therefore, a thicker PMMA passivation layer should be considered.

Post-annealing effect of low temperature atomic layer deposited Al2O3 on the top gate IGZO TFT

Electronical properties of top gate amorphous InGaZnO4 thin film transistors (TFTs) could be controlled by post-annealing treatment, which has a great impact on the Al2O3 insulator. To investigate the effect of post-annealing on Al2O3, Al/Al2O3/p-Si MOS capacitoras with Al2O3 films treated under various post-deposition annealing (PDA) temperature were employed to analysis the change of electrical properties, surface morphology, and chemical components by electrical voltage scanning, atomic force microscope (AFM), and x-ray photoelectron spectroscopy (XPS) technologies. After PDA treatment, the top gate TFTs had a mobility about 7 cm2 V−1 s−1 and the minimum subthreshold swing (SS) about 0.11 V/dec, and the threshold voltage (V th) shifted from positive direction to negative direction as the post-annealing temperature increased. Electrical properties of MOS capacitors revealed the existence of positive fixed charges and the variation of trap state density with increasing PDA temperature, and further explained the change of negative bias stress (NBS) stability in TFT. AFM results clarified the increased leakage current, degraded SS, and NBS stability in MOS capacitors and TFTs, respectively. XPS results not only illuminated the origin of fixed charges and the trap density variation with PDA temperatures of Al2O3 films, but also showed the O and H diffusion from Al2O3 into IGZO during post-annealing process, which led to the deviation of V th, the change of current density, and the negative V th shift after positive bias stress in TFTs.

Surface engineering of high-k polymeric dielectric layers with a fluorinated organic crosslinker for use in flexible-platform electronics.

High-k polymeric layers were prepared by combining various functional groups and were applied as gate dielectrics for practical organic field-effect transistors (OFETs). Crosslinking of the polymeric layers through UV-assisted organic azide fluorine-based crosslinkers induced dramatic improvements in the electrical performance of the OFET, such as field-effect mobility and bias-stress stability. Our synthesis and manufacturing method can be a useful technique for ensuring device operation stability and electrical property enhancement. With this analysis, we further applied our polymer-dielectric OFETs to flexible-platform-based electronic components, including unit OFETs and simple logic devices (NOT, NAND, and NOR gates). The outcomes of this research and development suggest a suitable method for the low-cost mass production of large-area flexible and printable devices, using a printing-based approach to replace current processes.

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

Improvement in Short-Channel Effects and Bias-Stress Stability of Vertical Thin-Film Transistors Using Atomic-Layer-Deposited In–Ga–Sn–O Channels

Boronization: A General Strategy for Rare Earth Oxides with Enhanced High-κ Gate Dielectric Performance.

Rare earth oxides (REOs) can be used as high-κ gate dielectrics that are at the core of electronic devices. However, a bottleneck remains with regard to obtaining high-performance REO dielectrics due to the serious hygroscopic issue and high defect states. Here, a general boronization strategy is reported to enhance the high-κ REO gate dielectric performance. Complementary characterization reveals that boronization is capable of reducing oxygen vacancies/hydroxyl defects in REOs and suppressing moisture absorption, leading to the improvement of leakage current, breakdown strength (up to 9 MV/cm), and capacitance-frequency stability. Furthermore, oxide transistors based on boronized REO dielectrics demonstrate state-of-the-art device characteristics with a high mobility of 40 cm2/V s, a current on/off ratio of 108, a subthreshold swing of 82 mV/dec, a hysteresis of 0.05 V, and superior bias stress stability.

An Amorphous Native Oxide Shell for High Bias-Stress Stability Nanowire Synaptic Transistor.

The inhomogeneous native oxide shells on the surfaces of III-V group semiconductors typically yield inferior and unstable electrical properties metrics, challenging the development of next-generation integrated circuits. Herein, the native GaOx shells are profitably utilized by a simple in-situ thermal annealing process to achieve high-performance GaSb nanowires (NWs) field-effect-transistors (FETs) with excellent bias-stress stability and synaptic behaviors. By an optimal annealing time of 5min, the as-constructed GaSb NW FET demonstrates excellent stability with a minimal shift of transfer curve (ΔVth ≈ 0.54V) under a 60min gate bias, which is far more stable than that of pristine GaSb NW FET (ΔVth ≈ 8.2V). When the high bias-stress stability NW FET is used as the chargeable-dielectric free synaptic transistor, the typical synaptic behaviors, such as short-term plasticity, long-term plasticity, spike-time-dependent plasticity, and reliable learning stability are demonstrated successfully through the voltage tests. The mobile oxygen ion in the native GaOx shell strongly offsets the trapping states and leads to enhanced bias-stress stability and charge retention capability for synaptic behaviors. This work provides a new way of utilizing the native oxide shell to realize stable FET for chargeable-dielectric free neuromorphic computing systems.

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

Fabrication and investigation of the electrical performance of nitrogenated bilayer ZnO:N/ZnO thin-film transistors

In this study, a bilayer ZnO:N/ZnO thin-film transistors (TFTs) was designed to improve both the performance and stability of single-layer ZnO TFTs, using the effects of N-treatment on oxygen vacancy (VO) and the interface trap density. Bilayer ZnO:N/ZnO films and related TFTs were fabricated via radiofrequency magnetron sputtering in a mixture of Ar and N2 gas at 150 °C. The electrical performance and bias-stress stability were systematically investigated. The bilayer ZnO:N/ZnO TFT exhibited a linear field-effect mobility of 13.6 cm2/Vs, high current on-to-off ratio (Ion/Ioff) of 1 × 107, small threshold voltage (Vth) of 2.6 V, and low subthreshold swing of 0.32 V/decade compared with single-layer undoped ZnO and ZnO:N TFTs. Moreover, ZnO:N/ZnO TFT exhibited small threshold voltage shifts (∆Vth) of 0.8 and –0.9 V according to positive bias illumination stress and negative bias illumination stress measurements, respectively. X-ray photoelectron spectroscopy analysis showed that the N-treatment passivated the VO defects, reduced the density of interface traps, and controlled the carrier concentration. Thus, the performance and stability of the ZnO:N/ZnO TFTs were improved. Therefore, ZnO:N/ZnO TFTs have good application prospects in transparent thin-film electronics and flat-panel displays.

Impact of In Situ Oxidation‐Resulted High‐k Passivation Layer on Device Stability and Mobility Improvement

The performance of nanoelectronic devices can be significantly improved using high‐k dielectric materials. However, the interface between the gate dielectric and channel can impact the device's stability and performance. To address this issue, a new approach is developed that involves incorporating high‐k dielectric into the channel via in situ oxidation of air‐sensitive 2D materials. Herein, the impact of HfSe2 thermal oxidation on the electrical properties of the MoS2 channel is investigated. The findings demonstrate that incomplete oxidation of HfSe2 on the MoS2 channel introduces significant border traps, leading to device performance degradation. In contrast, complete oxidation of HfSe2 leads to the formation of high‐k HfOx. The MoS2 field‐effect transistors capped by in situ thermally oxidized HfOx show a twofold enhancement in field‐effect mobility and improved gate bias stress stability. These findings suggest that the integration of high‐k dielectrics via in situ oxidation has great potential for high‐performance electronic device applications.