Bias Stress Instability Research Articles

Strain-dependent charge trapping and its impact on the operational stability of polymer field-effect transistors

Despite recent dramatic improvements in the electronic characteristics of stretchable organic field-effect transistors (FETs), their low operational stability remains a bottleneck for their use in practical applications. Here, the operational stability, especially the bias-stress stability, of semiconducting polymer-based FETs under various tensile strains is investigated. Analyses on the structure of stretched semiconducting polymer films and spectroscopic quantification of trapped charges within them reveal the major cause of the strain-dependent bias-stress instability of the FETs. Devices with larger strains exhibit lower stability than those with smaller strains because of the increased water content, which is accompanied by the formation of cracks and nanoscale cavities in the semiconducting polymer film as results of the applied strain. The strain-dependence of bias-stress stability of stretchable OFETs can be eliminated by passivating the devices to avoid penetration of water molecules. This work provides new insights for the development of bias-stable stretchable OFETs.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

Dependence of Positive Bias Stress Instability on Threshold Voltage and Its Origin in Solution-Processed Aluminum-Doped Indium Oxide Thin-Film Transistors.

The initial electrical characteristics and bias stabilities of thin-film transistors (TFTs) are vital factors regarding the practical use of electronic devices. In this study, the dependence of positive bias stress (PBS) instability on an initial threshold voltage (VTH) and its origin were analyzed by understanding the roles of slow and fast traps in solution-processed oxide TFTs. To control the initial VTH of oxide TFTs, the indium oxide (InOx) semiconductor was doped with aluminum (Al), which functioned as a carrier suppressor. The concentration of oxygen vacancies decreased as the Al doping concentration increased, causing a positive VTH shift in the InOx TFTs. The VTH shift (∆VTH) caused by PBS increased exponentially when VTH was increased, and a distinct tendency was observed as the gate bias stress increased due to a high vertical electric field in the oxide dielectric. In addition, the recovery behavior was analyzed to reveal the influence of fast and slow traps on ∆VTH by PBS. Results revealed that the effect of the slow trap increased as the VTH moved in the positive direction; this occured because the main electron trap location moved away from the interface as the Fermi level approached the conduction band minimum. Understanding the correlation between VTH and PBS instability can contribute to optimizing the fabrication of oxide TFT-based circuits for electronic applications.

Ultra-thin gate insulator of atomic-layer-deposited AlO x and HfO x for amorphous InGaZnO thin-film transistors

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x . Both kinds of high-k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x . Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs.

Improving OFF-State Bias-Stress Stability in High-Mobility Conjugated Polymer Transistors with an Antisolvent Treatment.

Conjugated polymer field-effect transistors are emerging as an enabling technology for flexible electronics due to their excellent mechanical properties combined with sufficiently high charge-carrier mobilities and compatibility with large-area, low-temperature processing. However, their electrical stability remains a concern. ON-state (accumulation mode) bias-stress instabilities in organic semiconductors have been widely studied, and multiple mitigation strategies have been suggested. In contrast, OFF-state (depletion mode) bias-stress instabilities remain poorly understood despite being crucial for many applications in which the transistors are held in their OFF-state for most of the time. Here, a simple method of using an antisolvent treatment is presented to achieve significant improvements in OFF-state bias-stress and environmental stability as well as general device performance for one of the best performing polymers, solution-processable indacenodithiophene-co-benzothiadiazole (IDT-BT). IDT-BT is weakly crystalline, and the notable improvements to an antisolvent-induced, increased degree of crystallinity, resulting in a lower probability of electron trapping and the removal of charge traps is attributed. The work highlights the importance of the microstructure in weakly crystalline polymer films and offers a simple processing strategy for achieving the reliability required for applications in flexible electronics.

Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator.

An ultrathin atomic-layer-deposited (ALD) AlOx gate insulator (GI) was implemented for self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Although the 4.0-nm thick AlOx exhibited ideal insulating properties, the interaction between ALD AlOx and predeposited a-IGZO caused a relatively defective interface, thus giving rise to hysteresis and bias stress instabilities. As analyzed using high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and the Hall measurement, the chemical reaction between the ALD precursor and a-IGZO is revealed. This was effectively prevented by preoxidizing a-IGZO with nitrous oxide (N2O) plasma. With 4 nm-AlOx GI and low-defect interfaces, high performance and stability were simultaneously achieved on SATG a-IGZO TFTs, including a near-ideal record-low subthreshold swing of 60.8 mV/dec, a low operation voltage below 0.4 V, a moderate mobility of 13.3 cm2/V·s, a low off-current below 10-13 A, a large on/off ratio over 109, and negligible threshold-voltage shifts less than 0.04 V against various bias-temperature stresses. This work clarifies the vital interfacial reaction between top-gate high-k dielectrics and amorphous oxide semiconductors (AOSs) and further provides a feasible way to remove this obstacle to downscaling SATG AOS TFTs.

Physico-Chemical Origins of Electrical Characteristics and Instabilities in Solution-Processed ZnSnO Thin-Film Transistors

We investigate the physico-chemical origins that determine the transistor characteristics and stabilities in sol-gel processed zinc tin oxide (ZTO) thin-film transistors (TFTs). ZTO solutions with Sn/(Sn+Zn) molar ratios from 0.3 to 0.6 were synthesized to demonstrate the underlying mechanism of the electrical characteristics and bias-induced instabilities. As the Sn/(Sn+Zn) ratio of ZTO is increased, the threshold voltage of the ZTO TFTs negatively shifts owing to the gradual increase in the ratio of oxygen vacancies. The ZTO TFTs with an Sn/(Sn+Zn) ratio of 0.4 exhibit highest saturation mobility of 1.56 cm2/Vs lowest subthreshold swing and hysteresis of 0.44 V/dec and 0.29 V, respectively, due to the desirable atomic states of ZTO thin film. Furthermore, these also exhibit outstanding positive bias stability due to the low trap density at the semiconductor-dielectric interface. On the other hand, the negative bias stress-induced instability gradually increases as the proportion of tin increases because the negative bias stress instability originates from the ionization of oxygen vacancies. These results will contribute to the optimization of the composition ratio in rare-metal-free oxide semiconductors for next-generation low-cost electronics.

Influence of oxygen-related defects on In-Ga-Sn-O semiconductor due to plasma-enhanced atomic layer deposition of Al2O3 for low-temperature thin-film transistor in terms of electrical properties

In-Ga-Sn-O (IGTO) thin-film transistors (TFTs) were fabricated with Al2O3 gate insulators by plasma-enhanced atomic layer deposition (PEALD) at a temperature of 150 °C. Electrical performances of IGTO TFTs were significantly affected by plasma conditions when Al2O3 was deposited on IGTO thin films by PEALD. Analyses of X-ray photoemission spectroscopy revealed that excessive oxygen species activated at high plasma power above 150 W were chemisorbed to IGTO films to create excess oxygen bonds such as oxygen interstitials (Oi). Distributions of density of states in IGTO bandgap extracted by photonic capacitance-voltage measurement matched well with positive bias stress (PBS) instability of TFTs. Split-oxygen interstitials [Oi (split)] first created on IGTO by oxygen plasma might migrate to the octahedral site by a constant high gate bias to form octahedral-oxygen interstitials [Oi2- (oct)] by capturing electrons under PBS and reside deep states. Significant changes of subthreshold slope in I-V characteristics during the recovery time after removing PBS indicated that these octahedral-oxygen interstitials such as Oi (oct) and Oi2- (oct) obviously originated from Oi (split) initially formed by plasma and that Oi (oct) defects created by a relaxation process acted as a neutral acceptor-like state above Fermi level and deteriorated electrical properties of IGTO TFT.

Nonuniform Mechanism for Positive and Negative Bias Stress Instability in β-Ga2O3 MOSFET

In this article, we experimentally study the instability of the key electrical characteristic for the fabricated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\beta }$ </tex-math></inline-formula> -Ga2O3 MOSFET under positive bias stress (PBS) and negative bias stress (NBS), such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\mathrm {TH}}}$ </tex-math></inline-formula> ), ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{{\mathrm {on}}}$ </tex-math></inline-formula> ), subthreshold slope (SS), and hysteresis. An ionized traps model is proposed to explain the instability, which depicts the traps and interfaces states capturing/releasing electrons from the channel. We find nonuniform instability mechanisms. Under the PBS of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{GS} = 4$ </tex-math></inline-formula> V for 1000 s, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\mathrm {TH}}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{{\mathrm {on}}}$ </tex-math></inline-formula> are increased by 0.8 V and 19%, respectively. The constant interface state density indicates that this instability is caused by border traps in the gate oxide capturing electrons from channel. For the NBS of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{GS} = -4$ </tex-math></inline-formula> V for 1000 s, the variation in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\mathrm {TH}}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{{\mathrm {on}}}$ </tex-math></inline-formula> is −0.54 V and −8.8%, respectively. The instability is attributed to both the border traps and interface states, and the net increase in activated interface states is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.25\times10$ </tex-math></inline-formula> 11 cm−2 extracted from hysteresis. Unlike the PBS, the interface states release electrons to bulk traps, and thus the activated interface state density changes. A good agreement with experimental results shows that the proposed model could accurately describe the instability mechanism under both PBS and NBS. These results provide guidance for identifying defects, optimizing device structure, and fabrication process to improve the reliability of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\beta } $ </tex-math></inline-formula> -Ga2O3 MOSFET.

Competition between heating and cooling during dynamic self-heating degradation of amorphous InGaZnO thin-film transistors

The dynamic self-heating (SH) instability of a-InGaZnO (a-IGZO) thin-film transistors (TFTs) was systematically investigated under static drain bias and pulsed gate voltage. The a-IGZO TFTs exhibited three distinct degradation stages, including a slightly positive shift of threshold voltage (ΔVth), then a gradually negative ΔVth, and finally an accelerated negative shift leading to normally-on characteristics. The underlying mechanisms were clarified to be SH-enhanced positive bias stress (PBS) instability, SH-generated donor defects, and the donor-populated central channel, respectively. By changing the duty ratio, frequency, peak, and base periods of gate pulses. The competition between heating and cooling periods was found to dominate the behavior and degree of dynamic SH degradations, suggesting a feasible instability-relieving method by sophisticatedly adjusting the dynamic operating conditions.

Excessive Oxygen Peroxide Model‐Based Analysis of Positive‐Bias‐Stress and Negative‐Bias‐Illumination‐Stress Instabilities in Self‐Aligned Top‐Gate Coplanar In–Ga–Zn–O Thin‐Film Transistors (Adv. Electron. Mater. 5/2022)

Bias-Stress Instability In article number 2101062, Sungju Choi, Hyuck-In Kwon, Dae Hwan Kim, and colleagues present an excess oxygen peroxide model, which simultaneously explains the positive-bias-stress and the negativebias-illumination-stress instabilities in commercial self-aligned top-gate coplanar indium-gallium-zinc oxide thin-film transistors. This model is verified by the effect of oxygen content on the generation and annihilation of subgap states and is essential to designing highly stable oxide thin-film transistors.

Bias-stress instabilities in low-temperature thin-film transistors made of Al2O3 and ZnO films deposited by PEALD

Thin film transistors (TFT) were fabricated by plasma-enhanced atomic layer deposition (PE-ALD) of aluminum oxide (Al2O3) and zinc oxide (ZnO) on glass substrates at 70 °C. The thicknesses of the Al2O3 (gate dielectric) and ZnO (n-type semiconductor) were 25 and 60 nm, respectively. Prior to Al2O3 deposition Cr/Au gate contacts were patterned using photolithography. Photolithography was also used to define aluminum source and drain contacts with thickness of 200 nm. The W/L ratio of the fabricated transistors was varied between 1 and 8 by varying the channel length L (40, 20 10 and 5 μm), while the channel width W was kept constant to 40 μm. Capacitance-voltage measurements revealed good uniformity of the Al2O3 layer with a dielectric constant value of ~8. The sheet resistance of the ZnO layer was found to be ~2400 Ω/sq. The TFT electrical characterization showed that the saturation mobility does not depend substantially on W/L ratio and had values between 0.82 and 1.1 cm2/V-s, while the subthreshold slope varied between 190 and 207 mV/dec. Moreover, a high on/off current ratio of ⁓107 was determined. The threshold voltage (Vth) instability was also characterized by positive and negative bias stress leading to a Vth shift of about −0.3 V and − 0.8 V, respectively.

Total Subgap Range Density of States-Based Analysis of the Effect of Oxygen Flow Rate on the Bias Stress Instabilities in a-IGZO TFTs

In this study, the oxygen flow rate (OFR) dependence of negative bias illumination stress (NBIS) and positive bias stress (PBS) in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices was investigated. Unlike in previous studies, our study simultaneously considered and analyzed the bias stress-induced degradation mechanisms by charge trapping and defect creation. NBIS and PBS instability were measured according to the OFR splits of bottom-gate (BG) IGZO TFTs and the behavior of full subgap range density of states (DOS) was experimentally tracked with especial emphasis on deep-level oxygen vacancy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {O}}$ </tex-math></inline-formula> ) peak. It was found that the observed DOS variation was consistent with the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {O}}$ </tex-math></inline-formula> ionization model during NBIS. In addition, the threshold voltage shift by charge trapping ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T,CT}}$ </tex-math></inline-formula> ) and the threshold voltage shift by defect creation, i.e., change of DOS, ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T,DOS}}$ </tex-math></inline-formula> ) were separated and extracted through the subthreshold slope decomposition method. After NBIS, the threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T}}$ </tex-math></inline-formula> ) was composed of a component by charge trapping and a component with the ionization of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {O}}$ </tex-math></inline-formula> . After PBS, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T}}$ </tex-math></inline-formula> was dominated by a component arising due to charge trapping. Fitting through the stretched exponential function (SEF) was performed for each separately extracted <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T}}$ </tex-math></inline-formula> , and the activation energy for each <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T}}$ </tex-math></inline-formula> was extracted using the inverse Laplace transform method through the extracted <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{\text {T0}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> . Activation energy by charge trapping and DOS was extracted from NBIS and PBS, respectively. As a result of simultaneously considering the two degradation mechanisms, the extracted activation energy was located between the previous values. Experimentally extracted sets of DOS-specific parameters before and after bias stress were applied to technology computer-aided design (TCAD) simulations. Accurate reproduction of TFT current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> ) curves before and after bias stress and recovery suggests that the methodology and parameter set used in this study are reasonable and potentially useful for a more robust and systematic analysis of the bias stress-induced instability in a-IGZO BG TFTs.

Unintended Carbon-Related Impurity and Negative Bias Instability in High-Mobility Oxide TFTs

Amorphous oxide semiconductors (AOS) with high-mobility (>40 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs) have recently become common for next-generation displays. While several candidates have been proposed, their practical use remains unclear because of their low reliability originating from bias stress instability such as negative bias stress (NBS) and positive bias stress (PBS). This study shows that CO-related impurity is a major source of NBS instability in amorphous InSnZnO (ITZO), a representative high-mobility AOS. CO-related impurity is formed at the surface of the ITZO layer after the photolithography process, according to thermal desorption spectroscopy and hard X-ray photoemission spectroscopy studies. It is shown that by using a simple method of UV ozone treatment at room temperature to remove these CO-related impurities, a high performance ITZO TFT with mobility of ~ 50 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and excellent bias stability, NBS (at -20 V, 3600 s): -0.25 V, PBS (+20 V, 3600 s): 0.15 V, can be realized. Almost the same results are obtained for Sn-free IZO-TFTs with mobility of ~70 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs but the NBS instability caused by CO-related impurity does not appear for IGZO TFTs. This finding suggests that the bias stress instability by CO-related species is sensitive to high mobility AOS-TFTs.

Reducing the Threshold Voltage Instability of β-Ga2O3 Nanobelt Field-Effect Transistors Using Ozone Treatment

β-Ga2O3 is a promising semiconducting material for next-generation power devices owing to its wide bandgap (4.8 eV), high breakdown electric field (8 MV/cm), and good thermal stability. β-Ga2O3 has a monoclinic crystal structure with weak covalent bonding along the direction of (100), so bulk β-Ga2O3 can be exfoliated into ultra-thin flakes, which can be integrated with van der Waals materials. An example of the application is metal-insulator-semiconductor field-effect transistors (MISFETs) using h-BN as a gate dielectric. H-BN has an atomically flat surface without dangling bond, minimizing interfacial states between the channel and insulator layer. Moreover, the high thermal conductivity of h-BN (30 W/m·K along the c-plane) makes heat management easier (cf. SiO2: 1.4 W/m·K). Therefore, β-Ga2O3/h-BN MISFETs are expected to enhance device performance with a synergetic effect of both materials.However, there are remaining reliability issues about the gate-bias stress instability (BSI), the temporary or permanent degradation of electrical properties from gate bias stress (ex. threshold voltage, field-effect mobility, on/off ratio). β-Ga2O3 FETs have been developed for high voltage operation in harsh environments, so that suppression of BSI is required. BSI is mainly attributed to charge trapping in the channel, channel/dielectric interface, or dielectric layer under gate-bias stress. In this work, we tried to reduce bias-stress instability of β-Ga2O3/h-BN MISFETs by UV-O3 treatment. Numerous reports demonstrated the annealing of oxygen-related defects by UV-O3 treatment in oxide-based materials. Therefore, UV-O3 treatment was expected to also work on β-Ga2O3.First, β-Ga2O3 (200-300 nm) and h-BN (40-50 nm) flakes were exfoliated from each bulk crystal with adhesive tape. H-BN flake was dry-transferred on SiO2/p++Si substrate, and subsequently β-Ga2O3 flake was stacked on h-BN. The source, drain, and gate electrodes (Ti/Au 50 nm/100 nm) were defined by e-beam lithography, followed by e-beam evaporation and lift-off processes. Bias-stress characteristics were systematically measured by Measure-Stress-Measure (MSM) method—repeating the sequence of 1) IDS-VGS, 2) VGS stress, 3) IDS-VGS sweep. β-Ga2O3/h-BN MISFET was UV-O3 treated using a commercial UV-O3 cleaning system (PSD-UV, Novascan Technologies, Ames, IA, USA). By following bias-stress characteristics measurement, we could observed reduced shifts of electrical properties regarding as annealing effect on oxygen-related defect by UV-O3 treatment. This work grants facile way to achieve β-Ga2O3 FETs stable to stress and open up new opportunities for the practical implementation of β-Ga2O3 power device. The details of methods and results will be presented at the conference.

Stabilizing solution-processed metal oxide thin-film transistors via trilayer organic–inorganic hybrid passivation

Solution-processed amorphous metal oxide semiconductors (AOSs) are promising candidates for printed electronics. However, process durability and bias stress instability issues still hinder their practical applications. Here, a poly(methyl methacrylate)/parylene/AlOx hybrid passivation approach was developed for AOS thin-film transistors (TFTs) to overcome these challenges. Notably, AlOx was successfully formed without degrading the AOS TFTs owing to the polymer buffer layers. The hybrid passivation approach ensured the satisfactory stabilization of the TFTs under bias stress owing to the high isolation effect, which could prevent the penetration of environmental molecules. This passivation method can facilitate the application of solution-processed AOSs in integrated circuits.

Bias stress instability in multilayered MoTe 2 field effect transistors under DC and pulse‐mode operation

Here, bias stress instability on multilayered MoTe2 field effect transistors (m-MoTe2 FETs) with encapsulation of hydrophobic polymers (cyclic transparent optical polymer) is systematically investigated under DC and pulse mode operation. During DC mode stress, the threshold voltage shift (ΔVth) under positive bias stress is at least three times larger than that of negative stress due to high hole barrier (∼0.57 eV), compared with electron barrier (∼0.18 eV). However, ΔVth in positive pulse mode stress is significantly reduced with decrease of a duty cycle, as compared with that of negative stress. With isolation from external gas ambient effects such as H2O and O2, shallow electron traps in multilayered MoTe2 field effect transistors are identified as one of strong candidates to cause bias polarity dependency on ΔVth in pulse mode. Moreover, recovery time for traps, involved during positive bias stress, is six times faster than that of negative stress, substantiating that shallow electron traps and their fast detrapping are one of key origins. In practice, optimisation of pulse mode operation via bipolar switching can be potentially utilised for minimisation of device instability during the operation of multilayered MoTe2 field effect transistors devices and their circuits.

Time-Dependent Threshold Voltage Instability Mechanisms of p-GaN Gate AlGaN/GaN HEMTs Under High Reverse Bias Conditions

In this article, we experimentally investigate the degradation mechanisms of GaN high-electron mobility transistors (HEMTs) with p-type gate during long-term hightemperature reverse bias (HTRB) stress and negative bias temperature instability (NBTI) stress. Based on a number of stress/recovery experiments, we demonstrate that HTRB stress could lead to hole emission in the p-GaN layer, making threshold voltage (Vth) positively shift, while NBTI stress could result in detrapping at the AlGaN/GaN interface or the AlGaN layer and make Vth negatively shift. It is also found that the temperature rise can suppress the positive Vth shift and accelerate its recovery process in HTRB experiments.

Gate Bias Stress Instability and Hysteresis Characteristics of InAs Nanowire Field-Effect Transistors.

Because of the excellent electrical properties, III-V semiconductor nanowires are promising building blocks for next-generation electronics; however, their rich surface states inevitably contribute large amounts of charge traps, leading to gate bias stress instability and hysteresis characteristics in nanowire field-effect transistors (FETs). Here, we investigated thoroughly the gate bias stress and hysteresis effects in InAs nanowire FETs. It is observed that the output current decreases together with the threshold voltage shifting to the positive direction when a positive gate bias stress is applied, and vice versa for the negative gate bias stress. For double-sweep transfer characteristics, the significant hysteresis behavior is observed, depending heavily on the sweeping rate and range. On the basis of complementary investigations of these devices, charge traps are confirmed to be the dominant factor for these instability effects. Importantly, the hysteresis can be simulated well by utilizing a combination of the rate equation for electron density and the empirical model for electron mobility. This provides an accurate evaluation of carrier mobility, which is in distinct contrast to the overestimation of mobility when using the transconductance for calculation. All these findings are important for understanding the charge trap dynamics to further enhance the device performance of nanowire FETs.

Origin of performance improvement in solution-processed indium–gallium–zinc-oxide thin-film transistors having thin active layer and asymmetric dual gate structure

In this paper, we report the electrical characteristics of thin active layer indium–gallium–zinc-oxide thin-film transistors (IGZO TFTs) having an asymmetric dual gate structure. It was observed that the performance of IGZO TFTs significantly improved when the TFT is operated in the dual gate mode though the performance of the top gate mode shows very poor performance of low field-effect mobility and large subthreshold slope. We found that the channel electrons are coupled in the bulk region when the active layer is very thin, and top gate biasing provides additional electrons to the coupled channel region, which improves the electrical performance of dual gate mode IGZO TFTs. Bias stress instability measurements also indicate that dual gate mode IGZO TFTs show better stability compared to the other mode because coupled electrons are mainly formed in the bulk region, which reduce the effect of interfacial defect density of states. Therefore, the improvements of performance of dual gate electrode IGZO TFTs can be realized regardless of the relatively poor performance of the top gate mode.