Bias Control Circuit Research Articles

Influence of detector temperature on Doppler signal quality of laser Doppler velocimeter

Enhancing the quality of Doppler signal holds paramount importance for the utilization of Laser Doppler Veolcimeter in velocity measurement of high-speed vehicles, underwater vehicles, and aerial vehicles. This paper discusses the variation of Doppler signal and noise with bias voltage at different temperatures, ultimately deriving the relationship between the signal-to-noise ratio of Doppler signal and detector temperature as well as bias voltage. And a linear correlation is established between detector temperature and optimal bias voltage. Furthermore, A bias control circuit for temperature compensation is designed for maximizing signal-to-noise ratio of Laser Doppler Velocimeter under varying temperatures.

Series diode‐connected current mirror based linear and sensitive negative bias temperature instability monitoring circuit

AbstractScaling of technology has a severe impact on the reliability of semiconductor devices. Negative bias temperature instability (NBTI) is a dominant factor in reliability degradation in nano‐scale technology. It is an aging phenomenon, which degrades the p‐channel metal oxide semiconductor (PMOS) transistors over time. A large area of the system on chip is covered by static random access memory (SRAM) and thus the overall system performance greatly depends on the stability of SRAM. In this paper, we evaluate the effect of NBTI on 6T SRAM cell performance for the stress period of 10 years. The simulation results show that the write margin is increased by 3.356% whereas hold static noise margin (SNM), read SNM, and standby leakage current is reduced by 6.53%, 23.86%, and 13.42%, respectively. We also present a series diode‐connected current mirror‐based linear and sensitive NBTI monitoring circuit using n‐channel metal oxide semiconductor (NMOS) transistors only. Continuous monitoring of the NBTI effect without any bias generator or control circuit is vital for the proposed sensor circuit. We have developed the electrical equivalent model and mathematical model of the proposed sensor for the fair comparison of results obtained through simulation and modeling. The sensitivity of the sensor is 40.6 μV/nA, and the sensor output voltage has a temperature variation of 20 μV/°C.

Low Power, Wide Range Synthesizer for 534 MHz–18.56 GHz Band with FoM of − 192.45 dBc/Hz

A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.

Proposal and Verification of Auto Calibration Technique for Bias Control Circuit Connecting to Built-In Optical Power Monitor in Imperfect IQ-Modulator

We show that imperfection in an IQ-modulator degrades the accuracy of the auto bias control (ABC) circuit connected to the modulator's complementary port. Theoretical analyses show that the IQ-modulator constructed by a nested Mach-Zehnder modulator with a low extinction ratio can distort a constellation of modulated light observed at the complementary port. We propose an auto calibration technique for the ABC circuit that can effectively suppress this degradation. Experimental results using 32-Gbaud, 16-QAM signals showed the measured Q-factor improved by 0.5dB with our proposed technique.

Optical single-sideband polarization modulator based on Sagnac interferometers and its applications in radio-over-fiber systems

A novel scheme to implement an optical single-sideband (OSSB) polarization modulator (PolM) is proposed and theoretically demonstrated in this paper. The proposed OSSB-PolM is based on the phase modulation technique in two consecutive Sagnac interferometers (SIs). It is shown that by applying four equal-power radio frequency (RF) signals with appropriate phases to electro-optic modulators and aligning the polarization state of the modulated signal in the proper direction, an OSSB-PolM signal will be generated. The proposed scheme can find many microwave photonic (MWP) applications. To show this, an OSSB modulator with tunable optical carrier-to-sideband ratio, an OSSB-suppressed carrier modulator/optical frequency shifter, and a full-ranged MWP phase shifter are proposed and demonstrated. The proposed structure includes several important advantages. For instance, the system is free from the limitations caused by optical/electrical filters. Since the propagating lights in an SI traverse the identical optical path in clockwise and counterclockwise directions, the system is immune to environmental perturbations. Furthermore, there is no need for a bias control circuit, so the system has a stable operation. In addition, the proposed scheme can be extended to multichannel applications in array antennas. Theoretically, calculations have been verified by simulation results.

A novel wideband pattern reconfigurable antenna using switchable parasitic stubs

AbstractA novel printed wideband pattern reconfigurable antenna using electronically switchable parasitic stubs is presented in this communication. The proposed antenna is compact, made of a low‐cost FR‐4 substrate and operates from 1.88 to 2.55 GHz with −10 dB impedance bandwidth. This antenna used only two PIN diodes and a simple bias control circuit without any vias or dc lines. It has the feature of improved gain, efficiency and two opposite directional patterns radiated in positive or negative x‐axis in the azimuth plane. It has the group delay variations within 2 ns for the wideband operation. The proposed antenna was fabricated and validated for its pattern diversity performance.

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.

On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of pMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin, and word line write margin (WLWM). The O-ABB consists of standby leakage current ( ${I}_{{ddq}}$ ) sensor circuit, decision circuit, and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of ten years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM, and WLWM decreases by 10.55%, 8.55%, and 3.25%, respectively, in the absence of O-ABB, whereas hold SNM, read SNM, and WLWM decreases by only 0.47%, 1.15%, and 0.62%, respectively, if O-ABB is used to compensate the degradation.

A WCDMA Multiband Power Amplifier Module With Si-CMOS/GaAs-HBT Hybrid Power-Stage Configuration

This paper describes a newly developed Si/GaAs hybrid multiband power amplifier module (MB-PAM) that supports major quad wideband code division multiple access (WCDMA) bands (Bands 5, 8, 2, and 1) for handset applications. With four dies (two GaAs-HBT dies, one GaAs-HEMT die, and one CMOS die) and several surface-mount devices, the hybrid MB-PAM accommodates two amplifier chains and two single-pole double-throw HEMT band-select switches on a 5 mm $\,\times\, $ 5.5 mm laminate, covering 824–915 and 1850–1980 MHz. Each amplifier chain has two switchable signal paths corresponding to dual (high and low) power modes [high-power mode (HPM) and low-power mode (LPM)] for saving battery current in practical handset use. One of the main features of this MB-PAM is the integration of driver stages, RF switches, and their bias control circuits on the CMOS die for pursuing cost reduction. Only the two output power stages are fabricated in a GaA-HBT process. Measurements conducted under the condition of a 3.4-V supply voltage and a WCDMA (Third Generation Partnership Project Release 99) modulated signal are as follows. Owing to optimized linear design and broadband output matching design, the hybrid MB-PAM achieves a power-added efficiency (PAE) as high as 39%–40% at 28 dBm of output power ( ${ P}_{\rm out}$ ) over 824–915 MHz in the HPM while maintaining a $\pm {\hbox{5-MHz-offset}}$ adjacent channel leakage power ratio (ACLR1) to less than $-{\hbox{39 dBc}}$ . In the LPM, PAE of 15% at a ${ P}_{\rm out}$ of 17 dBm is obtained while ACLR1 of less than $-{\hbox{40 dBc}}$ is maintained. For 1850–1980 MHz, the MB-PAM delivers 35% of PAE with ACLR1 of less than $-{\hbox{40 dBc}}$ at 28 dBm of ${ P}_{\rm out}$ in the HPM and 15% PAE at 17.5 dBm of ${ P}_{\rm out}$ in the LPM.

Constant Excess Bias Control for Single-Photon Avalanche Diode Using Real-Time Breakdown Monitoring

A monolithic constant excess bias control circuit for single-photon avalanche diode (SPAD) in standard 0.18-μm CMOS technology is reported. The proposed real-time breakdown monitoring technique is incorporated into a passive-quenching-active-reset circuit. A sample-and-hold circuit samples the breakdown level of SPAD through well-defined sampling phase. Following the sample-and-hold circuit, the level shifter with voltage shifting defined by predetermined excess bias provides the reset voltage of SPAD. The design operates the SPAD under constant excess bias and effectively mitigates the impact of the process-voltage-temperature variation by maintaining the optimal excess bias condition.

Auto bias control and bias hold circuit for IQ-modulator in flexible optical QAM transmitter with Nyquist filtering

An Auto Bias Control (ABC) technique for the IQ-modulator of a flexible optical QAM transmitter is described. This technique can support various optical QAM signal formats with Nyquist filtering and electronic dispersion pre-compensation. 16, 32 and 64-QAM signals (21 Gbaud) are successfully generated, and all bias voltages are held to their optimum value even when signal format is changed.

적응형 바이어스 조절 회로를 사용한 무선에너지 전송용 고효율 전력증폭기

본 논문에서는 구동 증폭기와 Class-E 전력증폭기를 결합하여 높은 효율의 고이득 이단 전력증폭기를 구현하였다. 고효율 이단 Class-E 전력증폭기의 입력 단에 적응형 바이어스 조절 회로를 적용하여 낮은 입력 전력의 전력효율을 개선하였다. 최대출력인 40 dBm에서 고정 바이어스 전력증폭기와 적응형 바이어스 증폭기 둘 다 약 76 %의 효율을 갖는다. 하지만 적응형 바이어스 조절회로가 적용된 전력증폭기의 입력전력 6dBm 인가했을 때 효율은 약 70 %이고 고정된 바이어스 입력시에 효율은 약 50 %이다. 바이어스 조절을 통해 낮은 입력에서 높은 효율을 갖는 회로를 설계하였다.

A Photonic mm-Wave Frequency Sextupler Using an Integrated Mach–Zehnder Modulator with Three Arms

A novel photonic mm-wave frequency sextupling scheme based on an integrated Mach–Zehnder modulator with three arms is proposed in this article. Without any optical filter, a high-quality frequency sextupling mm-wave signal can be generated. Compared with mm-wave generation schemes based on traditional two-arm Mach–Zehnder modulators, the proposed scheme does not need DC bias and a complex electrical bias control circuit. Some non-ideal factors are taken into consideration to verify its performance, which proves that a slight deviation of the ideal values does not cause great degradation of the performance of the mm-wave generation scheme.

A Dual-Mode Power Amplifier With On-Chip Switch Bias Control Circuits for LTE Handsets

In this brief, we present a dual-mode (high and low) power amplifier (PA) for fourth-generation long-term evolution (LTE) handset applications using a device switching technique to improve the efficiency at low output power. In particular, the effects of the gate voltage variation of the input and output switches on the amplifier performances are described. In addition, a bias control circuit for a dual-mode PA, which can provide the correct voltage to the input and output switches and can be effectively controlled by the mode control voltage, is also proposed. The bias control circuit, the mode switch, and the PA are implemented with the integrated pseudomorphic high-electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) technology on the same chip (i.e., bipolar field effect transistor process). A dual-mode PA with a gain of 27.2 dB, PAE of 34.5%, a ACLRE-UTRA value of -31.2 dBc, and error vector magnitude (EVM) of 2.97% has been achieved in high-power mode; whereas a 22 dB of gain, PAE of 19%, a ACLRE-UTRA value of -31.6 dBc and EVM of 2.84% were measured in the low-power mode with LTE uplink signals.

Performance Assessment of Radio Links Using Millimeter-Wave Over Fiber Technology With Carrier Suppression Through Modulation Index Enhancement

We have proposed and experimentally demonstrated a new radio-over-fiber system technique generating optical millimeter-waves with central carriers suppressed by simply tuning the modulation index of an optical phase modulator without requiring any complicated bias control circuits or narrowband optical filters. Error-free transmission of the generated 40-GHz optical mm-wave with 2.5-Gb/s data over 10-km single mode fiber (SMF-28) and 3-m air distance was achieved. The experimental results were analyzed and compared with the traditional method that requires a specific carrier suppression optical filter. The power penalty caused by the crosstalk between wavelength division multiplexed (WDM) channels was experimentally measured and studied and was about 4 dB at a bit error rate (BER) of 10-9. The filter bandwidth requirement, achievable carrier suppression ratio, and harmonics fluctuation due to fiber dispersion were also theoretically analyzed.

Bias Control for Optical OFDM Transmitters

The optical orthogonal frequency-division multiplexing transmitter typically employs a quadrature modulator (QM) to achieve up-conversion for high-capacity long-haul transmission. Bias tracking of the QM is essential to minimize transmitter impairments and to maintain long-term stable operation. A dither-free bias control circuit is proposed to maintain optimum bias points of the QM. By monitoring the QM output optical power P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> , optimum bias points can be acquired and tracked via minimization of the statistics (mean and variance) of P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> . Numerical studies of the bias control circuit reveal a 3-σ residual bias error within 0.075-7π incurring a bias error induced Q <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> penalty of ~0.6 dB.

Analog Pre-Distortion Linearizer Using Self Base Bias Controlled Amplifier

An analog pre-distortion linearizer employing a radio frequency (RF) transistor with a self base bias control circuit is proposed. The self base bias control circuit extracts the envelope from the modulated input RF signal of the RF transistor and automatically controls its base current according to the extracted envelope. As a result, the proposed linearizer realizes positive gain deviation at high input power level. By adding a resistor between the RF transistor and the self base bias control circuit, the negative gain deviation can be derived. The design of the proposed lineaizer is described with taking the envelope frequency response of the self base bias control circuit into consideration. The fabricated linearizer achieves the adjacent channel power leakage ratio (ACLR) improvement of 8.1dB for a 2GHz-band, 10W-class GaAs FET high-power amplifier (HPA) with negative gain deviation for W-CDMA base stations. It also achieves the ACLR improvement of 8.3dB for a LDMOS HPA with positive gain deviation for the same application.

High-Current–High-Speed Dynamic Bias Control System Applied to a 100-W Wideband Push–Pull Amplifier

This paper presents a dynamic bias control system applied to a high power wideband amplifier. The amplifier used is based on a push-pull topology with LDMOS transistors and works in the 50-500 MHz frequency bandwidth. It delivers a nominal 100 W output power with 60% power-added efficiency (PAE) when it is fed with continuous signals. When it is driven by a 16QAM modulated signal, 6 dB input power back-off is necessary to keep an error vector measurement below 5%. This usual back-off technique results in lower PAE (43% in our case). By implementing the proposed bias control system, both 55% PAE and 5% EVM have been reached for 75 W average output power. The drain bias control circuit handles high currents and high voltages (7 A-28 V). The proposed implementation makes use of a class S modulator driven by a SigmaDelta modulator. Up to 1 Mbit/s envelope bit rate can be efficiently and accurately processed by using here dedicated circuits running at 20 MHz clock frequency.

Enhanced Operating Range of WDM PON Implemented by Using Uncooled RSOAs

We report on the operable ranges of temperature and wavelength for a 1.25-Gb/s wavelength-division-multiplexed passive optical network (WDM PON) implemented by using uncooled reflective semiconductor optical amplifiers (RSOAs). Both the gain and modulation bandwidth of the RSOA are substantially reduced at high temperatures. As a result, it is difficult to achieve the error- free operation at temperatures above 40degC. In order to mitigate this limitation, we implement a simple bias-control circuit, in which the bias current is controlled stepwise according to the operating temperature of the RSOA. Using this circuit, we extend the operable wavelength range of the RSOA-based WDM PON to ~55 nm in the temperature range of -20degC to 60degC.

Linearity Improvement of a Power Amplifier Using a Series LC Resonant Circuit

A radio frequency power amplifier microwave monolithic integrated circuit with a series LC resonant circuit as well as a bias control circuit for wide-band code division multiple access application is presented. The linearizer that consists of a series LC resonant circuit and base-emitter junction of a bias transistor operates as a diode rectifier circuit. A comparison between the circuits with and without the linearizer has been demonstrated. The power amplifier (PA) with the series LC resonant linearizer exhibits adjacent channel leakage ratio-1 (ACLR1) of -37.2 dBc at output power of 27 dBm, a 5.6 dB improvement compared to the circuit without the linearizer. The bias control circuit reduces consumed average dc current from 83 mA to 57 mA for efficiency improvement. The linearized PA exhibits 1-dB compression point (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB) of 29.3 dBm, power-added efficiency of 45.7%, and power gain of 20.6 dB at low quiescent current of 37 mA with a 3.4 V single supply.