Series diode‐connected current mirror based linear and sensitive negative bias temperature instability monitoring circuit

Abstract

AbstractScaling of technology has a severe impact on the reliability of semiconductor devices. Negative bias temperature instability (NBTI) is a dominant factor in reliability degradation in nano‐scale technology. It is an aging phenomenon, which degrades the p‐channel metal oxide semiconductor (PMOS) transistors over time. A large area of the system on chip is covered by static random access memory (SRAM) and thus the overall system performance greatly depends on the stability of SRAM. In this paper, we evaluate the effect of NBTI on 6T SRAM cell performance for the stress period of 10 years. The simulation results show that the write margin is increased by 3.356% whereas hold static noise margin (SNM), read SNM, and standby leakage current is reduced by 6.53%, 23.86%, and 13.42%, respectively. We also present a series diode‐connected current mirror‐based linear and sensitive NBTI monitoring circuit using n‐channel metal oxide semiconductor (NMOS) transistors only. Continuous monitoring of the NBTI effect without any bias generator or control circuit is vital for the proposed sensor circuit. We have developed the electrical equivalent model and mathematical model of the proposed sensor for the fair comparison of results obtained through simulation and modeling. The sensitivity of the sensor is 40.6 μV/nA, and the sensor output voltage has a temperature variation of 20 μV/°C.