The metal-ferroelectric-semiconductor (MFS) heterostructure has been fabricated using Bi3.25La0.75Ti3O12 (BLT) as a ferroelectric layer by sol-gel processing. The effect of annealing temperature on phase formation and electrical characteristics of Ag/BLT/p-Si heterostructure were investigated. The BLT thin films annealed at from 500°C to 650°C are polycrystalline, with no pyrochlore or other second phases. The C-V curves of Ag/BLT/p-Si heterostructure annealed at 600°C show a clockwise C-V ferroelectric hysteresis loops and obtain good electrical properties with low current density of below 2×10−8 A/cm2 within ±4 V, a memory window of over 0.7 V for a thickness of 400 nm BLT films. The memory window enlarges and the current density reduces with the increase of annealing temperature, but a annealing temperature over 600°C is disadvantageous for good electrical properties.