Baugh-Wooley Multiplier Research Articles

Design of Modified Booth’s Encoder Using SPST technique

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.

Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application

Capricious Digital Filter Design and Implementation Using Baugh–Wooley Multiplier and Error Reduced Carry Prediction Approximate Adder for ECG Noise Removal Application

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

AbstractMost error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

VLSI Design of Approximate Baugh-Wooley Multiplier for Image Edge Computing

A sort of digital circuit used to multiply two binary values is called a Baugh-Wooley multiplier. It is renowned for being more effective than other kinds of multipliers in terms of speed and gate count. You would normally start by creating a simple version of the circuit utilizing logic gates like AND gates, XOR gates, and half adders to simulate the Baugh-Wooley multiplier. The design would then be optimized utilizing methods like parallel processing, pipelining, and optimization algorithms to lower the overall gate count and boost the functionality of the circuit. Because of this, estimating a Baugh-Wooley multiplier would require a thorough knowledge of these elements as well as the specifications of the application. Verilog HDL is used to implement this design, and Modelsim 6.4 c is used to simulate it. The synthesis process tool from Xilinx measures performance.

State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing

Multiplication is the key crucial operation in realizing digital signal processing (DSP) functions. It is accomplished by using diverse multiplier architectures. Multiplication operation is furthermost basic and normally used action in the central processing unit (CPU). The multiplication operation is the most fundamental and commonly performed activity in the central processing unit (CPU). An efficient multiplier design should have a high speed, small area, and a low power consumption. Compact, efficient multipliers with minimal power dissipation are needed. The proposed paper provides a thorough inspection of multipliers such as the Array multiplier, Booth multiplier, column bypass multiplier, Baugh-Wooley multiplier, and Vedic multiplier based on their operational activities and working, as well as their benefits and limits. A comparison of these multipliers' performance parameters such as speed, area, power consumption, quantum cost, garbage generation and circuit complexity.

Comparative Computer Design of Four-bits Nanomultiplier

This paper presents a simulation circuit of a 4x4 Baugh–Wooley multiplier on a proposed one-bit full adder. The results included a comparison with other adders, an analysis of energy dissipation depending on temperature and dissipated power of the existing and proposed multipliers in mW. As a result, it was found that the proposed adder has better properties compared to similar ones. As a result of the work, the simulation circuit of the Baugh–Wooley multiplier 4x4 was performed, and the simulation result was obtained. Computer-edit simulate and design is performed in QCA DESIGNER software.

Approximate Computing Circuits for Embedded Tactile Data Processing

In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.

Design of Baugh–Wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis

Complementary metal oxide semiconductor (CMOS) is a low-power technology typically used in the efficient implementation of digital circuits. However, at nanodimensions, CMOS has problems due to its short channel effects and subthreshold leakage currents. These drawbacks can be overcome with quantum-dot cellular automata (QCA) which is one of the fastest nanotechnologies operated at THz rate. Thus, all digital circuits can now be implemented by QCA at the required nanoscale. This paper proposes a novel, energy-efficient and area-optimized 1-bit full adder design using QCA which provides efficient clocking, reduced cell count and reduced energy dissipation. The proposed design utilizes only 26 quantum cells in 0.02 µm2 area and has a reduction of 8% in number of cells, 75% in delay and 4% in energy dissipation at 1 K compared to the existing works. This innovative full adder design is used to implement a 4 × 4 Baugh–Wooley multiplier. The simulation results of the multiplier observed on QCADesigner 2.0.3 tool validate that the Baugh–Wooley multiplier designed with the novel 1-bit full adder yields better performance in terms of 9% reduction in area, 17.4% reduction in quantum cells used and reduced power dissipation of 2.44nW.

Comparative analysis of various types of multipliers for effective low power

Nowadays, low power VLSI multiplier with high frequencies shows an important role in the VLSI field. Analysis and comparison of different types of multipliers such as wallace tree, array and baugh wooley multiplier were conceded out in this design. The physical verification of all their substitute blocks was performed to prove their capability and suitability as a multiplier and to enhance low power through the size of the transistor. Design of multipliers to improve the production of the complex circuit and analysis of the multiplier is resolute by the partial product reduction. Using the three multipliers, power, area and speed could be simulated by using modelsim 5.5 e and Xilinx ISE 8.1 i and finally, the values could be analysed. Among the three multipliers, the speed and power consumption of the baugh wooley multiplier was the smallest although the array multiplier could be the finest for decreased area applications.

English

English

An efficient MAC design for image processing application

Objectives: An efficient MAC design is planned for 2’s complement numbers with no more than partial-product creation methodology and diminution tree, whereas the succeeding step trappings an extraordinary sign-conservatory solutions. Methods/Statistical Analysis: Accumulate operations form an important process in signal and image processing applications. To expand MAC execution, the basic way postponement can be diminished by embeddings an additional pipeline register, either in the interior the two rows or stuck between the twos and the final adder. Findings: The 16 bit MAC architecture is implemented using Baugh-Wooley (BW) multiplier with Twin precision concept. The proposed methodology is verified by implementing in a 16 x 16 MAC unit. The performance parameters extracted demonstrates that the proposed Modified Booth with Twin precision based 16 bit MAC demonstrates an area reduction of 45.3%, delay reduction of 30.8% and power saving of 60% when compared to the MAC architectures designed using Baugh-Wooley with twin precision multiplier. Application/Improvements: It performs better than the conventional MAC in all the aspects. Keywords: Baugh-Wooley Multiplier, MAC Design, Partial-Product, Sign-Conservatory Solutions, Twin Precision

Improved Baugh Wooley Multiplier Using Cadence Register Transfer Level Logic for Power Consumption

In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster than a conventional Baugh-Wooley multiplier. The Improved Baugh-Wooley multiplier consumes the power of 09.02 mW and area of 52426 μm2.

Comparative Analysis of different Algorithm for Design of High-Speed Multiplier Accumulator Unit (MAC)

Background/Objectives: Power consumption is one of the important designsin many digital signal processing applications, the main building blocks of the processor is Multiplier-Accumulator (MAC) unit. Methods/Statistical Analysis: In the present work, the Baugh-Wooley multiplier is implemented for improving the performance of MAC unit. The Baugh wooley multiplier is faster than the other multipliers like Array multiplier, Wallace tree multiplier, Booth multiplier. The MAC unit using Baugh-Wooley multiplier is implemented using 180nm technology in cadence virtuoso. Findings: The speed of MAC unit using Wallace tree multiplier is 93.6MHz and with Baugh wooley multiplier is 99.1MHz. The power consumption of the MAC unit using Wallace tree multiplier is 2.265mW and with Baugh wooley multiplier is 4.628mW. The results show that the MAC unit using Baugh wooley multiplier is faster than the Wallace tree multiplier. Application/Improvements: MAC unit processors. In future, we can implement MAC unit using Baugh wooley multiplier with apipelining technique such that the total power consumption will be less.

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices. This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. In this work, a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh-Wooley multiplier. The proposed single multiplier cell is able to perform addition of a 1 × 1 product with the sum and carry from the previous cell. This reversible multiplier cell is useful in building up regularity in the array multipliers. The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.

Implementation of Modified Booth Encoding Multiplier for signed and unsigned 32 bit numbers

This paper presents the design and implementation of Modified Booth encoding multiplier for both signed and unsigned 32 - bit numbers multiplication. The already existed Modified Booth Encoding multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Whereas the array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requirement of the modern computer system is a dedicated and very high speed unique multiplier unit for signed and unsigned numbers. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. Index Terms: Modified Booth Encoding multiplier, Baugh-Wooley multiplier, array multiplier, CSA, CLA Partial product, Signed-unsigned.

Faster and Energy-Efficient Signed Multipliers

We demonstrate faster and energy-efficient column compression multiplication with very small area overheads by using a combination of two techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using new hybrid adder structures proposed here. Based on the proposed techniques, 8-b, 16-b, 32-b, and 64-b Wallace (W), Dadda (D), and HPM (H) reduction tree based Baugh-Wooley multipliers are developed and compared with the regular W, D, H based Baugh-Wooley multipliers. The performances of the proposed multipliers are analyzed by evaluating the delay, area, and power, with 65 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multipliers are as much as 29%, 27%, and 21% faster than the regular W, D, H based Baugh-Wooley multipliers, respectively, with a maximum of only 2.4% power overhead. Also, the power-delay products (energy consumption) of the proposed 16-b, 32-b, and 64-b multipliers are significantly lower than those of the regular Baugh-Wooley multiplier. Applicability of the proposed techniques to the Booth-Encoded multipliers is also discussed.

Design of Efficient Complementary Pass Transistor based Modified Booth Encoder Array Multiplier

paper a method to build a faster array multiplier based on Radix 4 Modified Booth Encoder - which is broadly used for the signed multiplication applications- with less area and power is presented. This is achieved by optimizing the overall interconnection delay in the partial product array and by scheming the most efficient Full Adder and Booth Encoder in Complementary Pass Transistor Logic approach. The proposed array multiplier's performance in terms of delay, power and area is compared with conventional as well as Baugh-Wooley Multiplier. In order to optimize the power and area of the multiplier, a CPL Based MBE with standard partial product array is proposed and designed in full custom style. The use of efficient 10 Transistor based Full adders based on CPL logic ensures that the entire design is in CPL logic, which provides a regular outline with less interconnection intricacy.

Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrixmatrix multiplier. A comparison with similar structures has shown that the proposed structure performs better.

A Low-power and High-performance Radix-4 Multiplier Design Using a Modified Pass-transistor Logic Technique

This paper describes a 1-bit adder designed using the modified complementary pass transistor logic technique. The proposed adder was implemented in an 8 × 8 bit high radix multiplier circuit. This paper describes the proposed adder technique for obtaining high speed, lower area, less power dissipation and lower propagation delay. The multiplier circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Microwind 2 VLSI layout CAD tool. The parameter analyses were performed with a BSIM4 analyzer. Two unsigned multipliers were designed using the proposed modified complementary pass-transistor logic (CPL) adder cell, namely a Carry Save Array multiplier (CSA multiplier) and a Baugh-Wooley multiplier, for comparison with our proposed adder cell-based high radix multiplier. The proposed adder cell-based CSA multiplier and Baugh-Wooley multiplier, as well as other existing multipliers, were compared with the high radix multiplier circuit in terms of power dissipation, propagation delay, latency, throughput, Energy Per Instruction and area. Our proposed 1-bit adder and adder-based high radix multipliers demonstrated better performance than other published results.

0.69mW, 700MHz Novel 8x8 Digital Multiplier

In this paper we presents the design of low power i.e 0.69mW and 700MHz, 8 x 8-bit digital multiplier providing a better performance and lower power dissipation than the conventional linear array multipliers in two folds of speed and power consumption. The modified pair-wise and parallel addition algorithms (2) provide high speed multiplication and lower power dissipation in this work. The power performance of individual block is pre evaluated to identify the most power consuming element and attempt is to select the most efficient topology to reduce the power consumption of entire multiplier while maintaining the high operating frequency. The proposed multiplier has been designed and implemented employing Tanner 0.18 μm CMOS technology and analyzed using TSPICE. When the multiplier is targeted to a maximum operating frequency of 700 MHz at VDD equal to 1.8 V, it dissipates 0.69 mW. For comparison purposes a Baugh-Wooley multiplier is redesigned and optimized. The simulation results are compared showing superiority of proposed multiplier in both power and speed performance.