Abstract

In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices. This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done for designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. In this work, a new 5 × 5 reversible multiplier cell is proposed which will be useful in designing Baugh-Wooley multiplier. The proposed single multiplier cell is able to perform addition of a 1 × 1 product with the sum and carry from the previous cell. This reversible multiplier cell is useful in building up regularity in the array multipliers. The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.

Highlights

  • In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices to provide substitution for CMOS technology

  • We have proposed a reversible multiplier cell which can be efficiently used in the Baugh Wooley multiplier

  • This is the first 5 × 5 reversible multiplier cells proposed in the literature

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Summary

Introduction

In today’s digital era, developing digital circuits is bounded by the research towards investigating various nano devices to provide substitution for CMOS technology. As the nano devices are developed, the density of digital chips is being increased naturally seeking the solution for the power consumption and the heat dissipation developed by this power consumption. This scenario motivates the study of reversible computing field. Loss of one bit information dissipates at least KTln joules of energy in the form of heat, where the Boltzmann’s constant is represented by K and the absolute temperature is represented by T. H. Bennett’s research, the circuits built using reversible logic gates will prevent KTln joules of

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