Abstract
Objectives: An efficient MAC design is planned for 2’s complement numbers with no more than partial-product creation methodology and diminution tree, whereas the succeeding step trappings an extraordinary sign-conservatory solutions. Methods/Statistical Analysis: Accumulate operations form an important process in signal and image processing applications. To expand MAC execution, the basic way postponement can be diminished by embeddings an additional pipeline register, either in the interior the two rows or stuck between the twos and the final adder. Findings: The 16 bit MAC architecture is implemented using Baugh-Wooley (BW) multiplier with Twin precision concept. The proposed methodology is verified by implementing in a 16 x 16 MAC unit. The performance parameters extracted demonstrates that the proposed Modified Booth with Twin precision based 16 bit MAC demonstrates an area reduction of 45.3%, delay reduction of 30.8% and power saving of 60% when compared to the MAC architectures designed using Baugh-Wooley with twin precision multiplier. Application/Improvements: It performs better than the conventional MAC in all the aspects. Keywords: Baugh-Wooley Multiplier, MAC Design, Partial-Product, Sign-Conservatory Solutions, Twin Precision
Highlights
In Core technologies in multimedia and communique system, to increase the speed of the operation, a dedicated architecture is needed for these DSP operations without disturbing the ALU of the processor
In the proposed MAC architecture, the Modified Booth multiplier is used for generating the partial product rows
To further enhance the performance Twin precision concept is used in the partial product generation
Summary
In Core technologies in multimedia and communique system, to increase the speed of the operation, a dedicated architecture is needed for these DSP operations without disturbing the ALU of the processor. This project is done by concentrating on the high-speed and lower power of the MAC architecture. For the multiplier row making, a innovative personalized Booth encoding (MBE) scheme[1] to enhance the performance of usual MBE scheme, there are two drawbacks: 1) An supplementaryrow terms at the (n-2)th bit location; 2) Poor overall concert at the LSB-element compared with the non-Booth propose by means of TDM
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