Abstract

Nowadays, low power VLSI multiplier with high frequencies shows an important role in the VLSI field. Analysis and comparison of different types of multipliers such as wallace tree, array and baugh wooley multiplier were conceded out in this design. The physical verification of all their substitute blocks was performed to prove their capability and suitability as a multiplier and to enhance low power through the size of the transistor. Design of multipliers to improve the production of the complex circuit and analysis of the multiplier is resolute by the partial product reduction. Using the three multipliers, power, area and speed could be simulated by using modelsim 5.5 e and Xilinx ISE 8.1 i and finally, the values could be analysed. Among the three multipliers, the speed and power consumption of the baugh wooley multiplier was the smallest although the array multiplier could be the finest for decreased area applications.

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